Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop Laptop_Lenovo_Foxcon-S09
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S09 Block Diagram
SYSTEM DC/DC
MAX1999 36
INPUTS OUTPUTS
5V_S5
www.hocnghetructuyen.vn 3V_S5
Thermal DCBATOUT
Mobile CPU
5V_AUX
G768D 18 3D3V_AUX
CLK GEN Dothan T8 SYSTEM DC/DC
OZ824 37
ICS954226 03 04.05 MAX651018
INPUTS OUTPUTS
1D05V_S0
HOST BUS 400/533MHz DCBATOUT
1D5V_S0
RGB CRT
12 SC486 38
1D8V_S3
DCBATOUT
DDR2 Alviso GM LVDS LCD
XGA
0D9V_S0
400/533 13 MAXIM CHARGER
11 GML OZ8604
35
S-Video TV-OUT
06,07,08,09,10 12 INPUTS OUTPUTS
DMI I/F 100MHz BT+
19V 3.0A
DCBATOUT
PWR SW 5V_AUX
LPC BUS PCI BUS Cardbus CP2211 23
5V 100mA
LCD/BTN Audio DJ28
ENE CB851 CARDBUS
ONE SLOT CPU DC/DC
Ext /CB1410 22
23 SC450
AC'97 AC-Link 39
MIC In 27
CODEC 1394 INPUTS OUTPUTS
23
LineOut27 RTLALC655 Mini-PCI VCC_CORE
26
MODEM
1.0
ICH6-M 802.11 B/G 29
DCBATOUT
0.844~1.3V
27A
20
Intel LAN PCB LAYER
OP AMP LCI TXFM25 RJ45
82562GT 25 L1: Signal 1
Speaker27 TPA6017A2
27
24
L2: VCC
USB LPC BUS L3: Signal 2
USB XD BIOS
3 PORT L4: Signal 3
14.15.16.17
21 8/4Mb L5: GND
30
PATA KBC L6: Signal 4
ENE MXA
6999MP
391030 32
HDD ODD
SMBus EEPROM
(master) (slave) AT24C01A TECHNOLOGY COPR.
19 19
32
Touch INT_KB Title
Block Diagram
Pad 31 31 Document Number
S09 MAINBOARD
Rev
A
Date: Sunday, March 13, 2005 Sheet 1 of 45
A B C D E
Alviso Strapping Signals ICS954226 Spread Spectrum ICH6-M Integrated Pull-up
and Configuration page 7 Select page 3
and Pull-down Resistors
ICH6-M EDS 15851 1.5V1
Pin Name Strap Description Configuration
EE_DIN, EE_DOUT, GNT[3:0]
CFG[2:0] FSB Frequency Select 000 = Reserved Pin17/18
001 = FSB533 Byte 6b7 Byte 6b6 byte 6b5 Byte 6b4 Spread Mode Spread Amount% Mhz GNT[4]#/GPO[48], GNT[5]#/GPO[17],
101 = FSB400
011-111 = Reversed 1 0 0 0 Down 0.8 100 GNT[6]#/GPO[16], GPIO[25] ICH6 internal 20K pull-ups
4 CFG[3:4] Reversed 1 0 0 1 Down 1.25 100 LAD[3:0]#/FB[3:0]#, LAN_RXD[2:0],
4
CFG5 DMI x2 Select 0 = DMI x2 1 0 1 0 Down 1.75 100 LDRQ[0], LDRQ[1]/GPI[41],PME#,
1 = DMI x4 (Default)
0 = DDR II (Default) 1 0 1 1 Down 2.5 100 PWRBTN#, TP[3]
CFG6 DDR I / DDR II 1 = DDR I
1 1 0 0 Center +-0.3 100 (Default)
CFG7 CPU Strap 0= Reserved
1=Dothan (Default) 1 1 0 1 Center +-0.5 100
ACZ_BITCLK, ACZ_RST#, ACZ_SDIN[2:0], ICH6 internal 20K pull-downs
CFG8 Reversed 1 1 1 0 Center +-0.8 100
ACZ_SDOUT, ACZ_SYNC, DPRSTP#
1 1 1 1 Center +-1.25 100
CFG9 PCI Express Graphics 0=Reverse Lanes DPRSLPVR, EE_CS, SPKR,
Lane reverse option
1=Normal Operation
for layout convenience (Default) PCI Routing USB[7:0][P,N] SATALED# ICH6 internal 15K pull-downs
CFG10 Reversed
IDSEL IRQ REQ/GNT DD[7], DDREQ ICH6 internal 11.5K pull-downs
CFG11 Reversed
CB851 25 E 0 LAN_CLK ICH6 internal 100K pull-downs
00 = Reserved
CFG[13:12] XOR/ALL Z test 01 = XOR mode enabled
straps 10 = All Z mode enabled MiniPCI 21 C 1
11 = Normal Operation
(Default)
ICH6-M Strapping Options
3 CFG[14:15] Reversed
1394 19 E 3 REF FUNCTION DEFAULT OPTIONAL OVERRIDE 3
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled R275 No Reboot Dummy Reserved
(Default)
A16 Swap
CFG17 Reversed R279 Override Dummy Reserved
CFG18 GMCH core VCC 0 = 1.05V (For GML)
ICH6-M IDE Integrated Series
Select R282 Boot BIOS Dummy Reserved
CFG19 CPU VTT Select
1 = 1.5V (For GM)
Termination Resistors
0 = 1.05V (Default)
1 = 1.2V
CFG20 Reversed DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
SDVO SDVO Present 0 = No SDVO device present DDACK#, IORDY, DA[2:0], DCS1#,
CRTL_DATA (Default)
1= SDVO device present DCS3#, IDEIRQ
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal. I2C/SMB Addresses
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KBC Hardware Strap page 30 Device Address Bus
Clock Generator 1101 001x SMB_ICH_S0
2 PinNumber PinName Function 2
SO-DIMM0 1010 000x SMB_ICH_S0
125 A1 High:Enable the internal pull-up resistors on XIOCS [F:0] pins
Low:Disable the internal pull-up resistors on XIOCS [F:0] SO-DIMM1 1010 010x SMB_ICH_S0
Thermal Sensor 0111 101x SMB_KBC_S0
128 A4 High: Diasble DMPP(Recommended)
Low : Enable DMPP Battery 0001 000x SMB_KBC_S5
131 A5 High:Enable EMWB(Recommended for application using shared BIOS Antitheft 1010 000x SMB_KBC_S5
Low:Disable EMWB Light Sensor 0111 001x SMB_KBC_S0
11 GPIO05 High:Test Mode
Low:32KHz clock in normal running(Recommend)
12 GPIO06 High:Test Mode(KSOUT0~15 become DPLL internal data outputs,
KSO16 becomes internal power-on reset output
1 Low:Normal operation(Recommended) www.hocnghetructuyen.vn 1
105 GPIO20 High:Normal operation(Recommended)
TECHNOLOGY COPR.
Low:Enable ISP mode during which the RD#,WR#,MEMSEL#,A[20:0]
Title
andD[7:0}will be controlled by ISP COntriller
Table of content
Document Number Rev
S09 MAINBOARD A
Date: Tuesday, March 15, 2005 Sheet 2 of 45
5 4 3 2 1
3D3V_S0
3D3V_S0 FB1 FB L0603 180 Ohm
R1 R0603 3D3V_APWR_S0
0 +/-5% BC1 BC2 1 2 3D3V_CLKGEN_S0
4.7uF 0.1uF BC3 BC4 BC5 BC6 BC7 BC8 BC9 BC10
10V, Y5V, +80%/-20% * * 16V, Y5V, +80%/-20%
* 10uF
* 0.1uF 0.1uF
* * 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
C0805 C0402
C0805 C0402 C0402 C0402 C0402 C0402 C0402 C0402
10V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%
D
www.hocnghetructuyen.vn D
3D3V_S0
R2 R0603 3D3V_48MPWR_S0
0 +/-5% BC11 BC12
4.7uF 0.1uF
* *16V, Y5V, +80%/-20%
U1
C0805 C0402
10V, Y5V, +80%/-20%
3D3V_APWR_S0 37 54
VDDA CPU_STP# PM_STPCPUJ 15,39
3D3V_CLKGEN_S0 1 44 RN1 1 4 4P2R0402V CLK_CPU_BCLK 4
VDDPCI CPUT0 33
7 VDDPCI CPUC0 43 2 3 +/-5% CLK_CPU_BCLKJ 4
3D3V_S0 21 41 RN2 1 4 4P2R0402V CLK_MCH_BCLK 6
VDDPCIEX CPUT1 33
28 VDDPCIEX CPUC1 40 2 3 +/-5% CLK_MCH_BCLKJ 6
34 VDDPCIEX
36 CLK_XDP_CPU 1 TP1
R626 CPUT2_ITP/PCIEXT6 CLK_XDP_CPUJ 1 TP2
42 VDDCPU CPUC2_ITP/PCIEXC6 35
10K 48
+/-5% VDDREF RN3
ITP_EN 0=PCIEX_6 1=CPU_2_ITP LCDCLK_SS/PCIEX0T 17 2 3 4P2R0402V DREFSSCLK 7
R0402 3D3V_48MPWR_S0 11 18 33 1 4 +/-5%
SS_SEL 0=LCDCLK 1=PCIEX/free running VDD_48 LCDCLK_SS/PCIEX0C DREFSSCLKJ 7
Dummy
3.3V PCI clock output PCIEXT1 19
R6 33 R0402 +/-5% 56 20
C
29
22
PCLK_MINI
PCLK_PCM R7 33 R0402 +/-5% 3
PCICLK2/REQ_SEL
PCICLK3
** PCIEXC1
C
3D3V_S0 30 PCLK_KBC R8 33 R0402 +/-5% 4 22 RN4 2 3 4P2R0402V CLK_MCH_3GPLL 7
PCICLK4 PCIEXT2 33
28 CLK33_AUDIODJ R9 33 R0402 +/-5% 5 PCICLK5 PCIEXC2 23 1 4 +/-5% CLK_MCH_3GPLLJ 7
H/L: 100/96MHz
SS_SEL 9 24
SELPCIEX_LCDCLK#/PCICLK_F1 PCIEXT3
55 25
R12 R13
15 PM_STPPCIJ
15 CLK_ICHPCI R11 33 R0402 +/-5% ITP_EN 8
PCI/SRC_STP#
ITP_EN/PCICLK_F0
** PCIEXC3
10K 10K H/L : CPU_ITP/SRC7 26
+/-5% +/-5% SATACLKT
SATACLKC 27
R0402 R0402 39 VTT_PWRGDJ VTT_PWRGDJ 10
Dummy VTT_PWRGD#/PD RN6
PCIEXC4 30 2 3 4P2R0402V CLK_PCIE_ICHJ 15
R14 22R0402 +/-5% FS_A 12 31 33 1 4 +/-5%
15 CLK48_ICH USB_48/FS_A PCIEXT4 CLK_PCIE_ICH 15
ITP_EN
SS_SEL RN7 1 4 4P2R0402V 14 32
7 DREFCLK
33 2 3 +/-5% 15
DOT96T * PEREQ2#/PCIEXC5
33
R15 R16
7 DREFCLKJ DOT96C * PEREQ1#/PCIEXT5
10K 10K 11,17 SMBC_ICH 46
+/-5% +/-5% SCLK
11,17 B_SMBD_ICH 47 SDATA GND 13
R0402 R0402
*
*
Dummy BC13 50V, NPO, +/-5% X2_ICS 49 51
1D05V_S0 C0603 X1_ICS XOUT GND
50 XIN GND 45
2
33pF GND 29
R18 X1 BSEL0 53
1K BSEL1 REF1/FS_C/TEST_SEL
X-14D318MHz 16 FS_B/TEST_MODE GND 2
+/-5% 6
1
GND
*
*
R0402 BC14 R19 R0402 39
Dummy C0603 50V, NPO, +/-5% 475 +/-1% 52 IREF
REF0 GNDA 38
B 4 CPU_SEL0 R21 0 +/-5% R627 2.2K BSEL0 B
R0402 R0402 +/-5% 33pF R22 47R0402 +/-5%
15 CLK_ICH14
R24 FS_C ICS954226
7 MCH_BSEL0 R23 1K+/-5% 2.2K
R0402 +/-5%
R0402 *internal Pull-Up resistors
Dummy EMI capacitor
**internal Pull-Down resistor
1D05V_S0 BSEL0 R518 22R0402 +/-5% AC_CLK 26
CLK_ICH14 C1 10pF C0402 50V, NPO, +/-5% Dummy
********
R26
1K
To external AC'97 CLK PCLK_PCM C2 10pF C0402 50V, NPO, +/-5% Dummy
+/-5%
R0402 PCLK_MINI C3 10pF C0402 50V, NPO, +/-5% Dummy
Dummy
4 CPU_SEL1 R27 0 +/-5% BSEL1 CLK_PCIE_ICH R28 49.9 R0402 +/-1% CLK_CPU_BCLK R29 49.9 R0402 +/-1% PCLK_KBC C4 10pF C0402 50V, NPO, +/-5% Dummy
R0402 FS_B
R33 CLK_PCIE_ICHJ R30 49.9 R0402 +/-1% CLK_CPU_BCLKJ R31 49.9 R0402 +/-1% CLK_ICHPCI C5 10pF C0402 50V, NPO, +/-5% Dummy
7 MCH_BSEL1 R32 1K+/-5% 2.2K
R0402 +/-5% DREFSSCLKJ R34 49.9 R0402 +/-1% CLK_MCH_BCLK R35 49.9 R0402 +/-1% CLK48_ICH C6 10pF C0402 50V, NPO, +/-5% Dummy
R0402
Dummy DREFSSCLK R36 49.9 R0402 +/-1% CLK_MCH_BCLKJ R37 49.9 R0402 +/-1% CLK33_AUDIODJ C7 10pF C0402 50V, NPO, +/-5% Dummy
DREFCLK R38 49.9 R0402 +/-1% CLK_MCH_3GPLL R39 49.9 R0402 +/-1% AC_CLK C8 10pF C0402 50V, NPO, +/-5% Dummy
3D3V_S0
DREFCLKJ R40 49.9 R0402 +/-1% CLK_MCH_3GPLLJ R41 49.9 R0402 +/-1%
A R42 A
10K FS_C FS_B FS_A CPU
+/-5%
R0402 0 0 0 266M
FS_A 0 0 1 133M
0 1 0 200M TECHNOLOGY COPR.
R45 0 1 1 166M
10K 1 0 0 333M Title
+/-5% 1 0 1 100M
R0402
Dummy
1 1 0 400M Clock Generator
Document Number Rev
S09 MAINBOARD A
Date: Tuesday, March 15, 2005 Sheet 3 of 45
5 4 3 2 1
5 4 3 2 1
U2A TP3
1
1D05V_S0
6 B_H_AJ[31..3] B_H_AJ3 P4
A3# ADS# N2 B_H_ADSJ 6
B_H_AJ4 U4 L1
A4# BNR# B_H_BNRJ 6
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ADDR GROUP 0
B_H_AJ5 V3 J3
A5# BPRI# H_BPRIJ 6
B_H_AJ6 R3 R46
B_H_AJ7 V2 A6# 56
A7# DEFER# L4 H_DEFERJ 6
B_H_AJ8 W1 H2 B_H_DRDYJ 6 +/-5%
B_H_AJ9 T4 A8# DRDY# R0402
A9# DBSY# M2 B_H_DBSYJ 6
B_H_AJ10 W2
B_H_AJ11 Y4 A10# Place testpoint on
A11# BR0# N4 B_H_BREQJ0 6
B_H_AJ12 Y1 H_IERR# with a GND
CONTROL
D A12# D
B_H_AJ13 U1 A4 H_IERRJ 0.1" away
B_H_AJ14 AA3 A13# IERR#
A14# INIT# B5 H_INITJ 14
B_H_AJ15 Y3
B_H_AJ16 AA2 A15#
A16# LOCK# J2 B_H_LOCKJ 6
6 B_H_ADSTBJ0 U3 ADSTB#0 H_CPURSTJ 6
6 B_H_REQJ[4..0] RESET# B11 H_RSJ[2..0] 6
B_H_REQJ0 R2 H1 H_RSJ0 B_H_DJ[63..0] 6
B_H_REQJ1 REQ0# RS0# H_RSJ1
P3 REQ1# RS1# K1
B_H_REQJ2 T2 L2 H_RSJ2
B_H_REQJ3 REQ2# RS2#
P1 REQ3# TRDY# M3 H_TRDYJ 6 U2B
B_H_REQJ4 T1 REQ4#
K3
XTP/ITP SIGNALS
HIT# B_H_HITJ 6
B_H_AJ17 AF4 K4 B_H_DJ0 A19 Y26 B_H_DJ32
A17# HITM# B_H_HITMJ 6 D0# D32#
B_H_AJ18AC4 Put these Caps near B_H_DJ1 A25 AA24 B_H_DJ33
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