Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop Laptop_Lenovo_Foxcon-W06N
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W06N Block Diagram MXM VGA Card
TMDS DVI
CONN SYSTEM DC/DC
15
www.hocnghetructuyen.vn Thermal MAX1999 40
Mobile CPU G768D 21 VRAM*4 RGB
CRT INPUTS OUTPUTS
CLK GEN Yonah T8 CONN
14
5V_S5
3V_S5
DCBATOUT
ICS954226 03 C1 Stepping 04.05 MAX651021 LVDS 5V_AUX
LCD 3D3V_AUX
XGA/SXGA+
HOST BUS 533 / 667 MHz M24-P/NV43 16 SYSTEM DC/DC
PCI Express MAX1845 38
PM DB S-Video
TV-OUT INPUTS OUTPUTS
DDR2
Calistoga SDVO CH7307 DB DCBATOUT
1D05V_S0
400/533/667Mhz RGB 15 1D5V_S0
11,12 GM Maxim 8550 39
LVDS
GML S-Video DCBATOUT
1D8V_S3
0D9V_S0
B1 Stepping 06,07,08,09,10
DMI I/F 100MHz Switch MAXIM CHARGER
MAX1645B
LPC PWR SW DB
LCD/BTN Audio DJ31 CP2211 25
PCI BUS Cardbus/1394/ INPUTS OUTPUTS
CARDBUS
AC'97 AC-Link CardReader ONE SLOT 26
BT+
18V 4.0A
DCBATOUT
S/P DIF30 CODEC ENE CB810 24,25 5V_AUX
CardReader
ALC655
29 7 in 1 26 5V 100mA
Line In30 MODEM CPU DC/DC
MDC Card Mini-PCI 1394*1
MIC In 30 23 ICH7-M 802.11A/B/G 28 26
SC452
37
INPUTS OUTPUTS
LineOut30 OP AMP
VCC_CORE
GMT1421b
30
PCB LAYER DCBATOUT
Speaker30 LAN L1: Signal 1
0.844~1.3V
RTL8100CL TXFM RJ45DB 27A
DB L2: GND
PWR SW 27
22 LPC BUS L3: Signal 2 SYSTEM DC/DC
MAX1993 DB
PCI Express B2 Stepping
L4: Signal 3 (external VGA Core)
17.18.19.20
L5: VCC INPUTS OUTPUTS
PCI-E Card
USB*6
SATA
KBC XD BIOS LPC
PATA
22 NS L6: Signal 4
ENE DCBATOUT 1D2V_S0
87381 DEBUG
4Mb CONN.
34 KB3910
32 35 35
HDD
BlueTooth USB
4 PORT
DB (master)
22 ODD FOXCONN ND2
Touch INT_KB Title
HDD (slave) FIR 34 PS2 Pad 33
22 33
Block Diagram
Size Document Number Rev
Reserve A3
W0 6N Sheet SA
Date: Saturday, February 19, 2005 1 of 44
A B C D E
Calistoga Strapping Signals ICS954226 Spread Spectrum ICH7-M Integrated Pull-up
page 3
and Configuration page 7 Select and Pull-down Resistors ICH7-M EDS 16971 1.0V1
Pin Name Strap Description Configuration EE_DIN,EE_DOUT, GNT[3:0]
Pin17/18 GNT[4]#/GPO[48], GNT[5]#/GPO[17],
CFG[2:0] FSB Frequency Select 001 = FSB533 Byte 6b7 Byte 6b6 byte 6b5 Byte 6b4 Spread Mode Spread Amount% Mhz
011 = FSB667 GNT[6]#/GPO[16], GPIO[25] ICH7 internal 20K pull-ups
Others = Reversed 1 0 0 0 Down 0.8 100
LAD[3:0]#/FB[3:0]#, LAN_RXD[2:0],
1 0 0 1 Down 1.25 100
4 CFG[3:4] Reversed
1 0 1 0 Down 1.75 100
LDRQ[0], LDRQ[1]/GPI[41],PME#, 4
CFG5 DMI x2 Select 0 = DMI x2 PWRBTN#, TP[3]
1 = DMI x4 (Default) 1 0 1 1 Down 2.5 100
0 = Moby Dick
CFG6 NB strap 1 = Calistoga (Default) 1 1 0 0 Center +-0.3 100 (Default) SATALED# ICH7 internal 15K pull-ups
CFG7 CPU Strap 0= Reserved 1 1 0 1 Center +-0.5 100 ACZ_BITCLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs
1=Mobility (Default)
1 1 1 0 Center +-0.8 100 ACZ_SDOUT, ACZ_SYNC, DPRSTP#
CFG8 Reversed
1 1 1 1 Center +-1.25 100 DPRSLPVR, EE_CS,SPKR,
SPI_ARB, SPI_CLK,
CFG9 PCI Express Graphics 0=Reverse Lanes
Lane reverse option 1=Normal Operation PCI Routing USB[7:0][P,N] ICH7 internal 15K pull-downs
for layout convenience (Default)
IDSEL IRQ REQ/GNT DD[7], DDREQ ICH7 internal 11.5K pull-downs
CFG10 Reversed
CFG11 Reversed CB810 25 E 0 LAN_CLK ICH7 internal 100K pull-downs
CFG[13:12]
Reversed MiniPCI 21 G 1 ICH7-M Strapping Options
Reversed This signal enables the internal VccSus1_5V suspend
Reversed
LAN 23 F 2 regulator when connected to VccRTC. When connected to
CFG[14:15] GND, the internal regulator is disabled.
3 Reversed 1394 19 E 3 INVTVRMEN To enable internla VccSus1_5V VRM pull signal to 3
VccRTC via 330Kohm
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled
(Default)
ICH7-M IDE Integrated Series The signal has a weak internal pull-down. If the
CFG17 Reversed
GMCH core VCC
Termination Resistors signal is sampled high, this indicates that the
system is strapped to the "No Reboot" mode (ICH7M
0 = 1.05V (Default)
CFG18 Select 1 = 1.5V will disable the TCO Timer system reboot feature).
The status of this strap is readable via the NO
0 = Normal(Default) DD[15:0], DIOW#, DIOR#, DREQ, SPKR REBOOT bit. NOTE: Please refer to ICH7M EDS Rev0.5
CFG19 DMI Lane Reversal 1 = Lanes Reversal approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#, (or latest) for all ICH7M Strap details.
0= Only SDVO or PCIEx1 is operational ( default)
CFG20 1= SDVO and PCIE x1 are operating DCS3#, IDEIRQ
simultaneously via the PEG port
Pin Name Strap Description Configuration
SDVO 0 = No SDVO device present
CRTL_DATA SDVO Present 1= SDVO device present GNT3# Top-Block Swap Internal Pull-up for
(Default) Override top-block swap mode.
NOTE: All strap signals are sampled with respect to the leading
edge of the Alviso GMCH PWORK In signal.
www.hocnghetructuyen.vn LINKALERT# Reversed
SPKR No Reboot Internal pull-down to indicate system
is strapped to the no reboot more.
KBC Hardware Strap INTVRMEN VccSus1_05 VRM
Enable/Disable.
0 = Disable
1 = Enable
(Default)
GPIO25 Reserved
2 PinNumber PinName Function 2
EE_CS Reversed
125 A1 High:Enable the internal pull-up resistors on XIOCS [F:0] pins GNT5# Boot BIOS 01 = SPI
/GPIO17#. Destination
Low:Disable the internal pull-up resistors on XIOCS [F:0] GNT4# Selection
10 = PCI
/GPIO48.
11 = LPC (Default)
EE_DOUT Reversed
128 A4 High: Diasble DMPP(Recommended)
ACZ_SDOUT XOR Chain Entrance 0 = Allow XOR Testing (Default)
Low : Enable DMPP 1 = Not Allow
ACZ_SYNC PCI-E Port CFG Bit 0 Reversed
131 A5 High:Enable EMWB(Recommended for application using shared BIOS GPIO16/ Reversed
DPRSLPVR
Low:Disable EMWB
SATALED# Reversed
11 GPIO05 High:Test Mode REQ[4:1]# XOR Chain Selection Not available in Datasheet Yet
Low:32KHz clock in normal running(Recommend) TP3 XOR Chain Entrance Not available in Datasheet Yet
12 GPIO06 High:Test Mode(KSOUT0~15 become DPLL internal data outputs,
KSO16 becomes internal power-on reset output
1 Low:Normal operation(Recommended) 1
105 GPIO20 High:Normal operation(Recommended)
Low:Enable ISP mode during which the RD#,WR#,MEMSEL#,A[20:0] FOXCONN ND2
Title
andD[7:0}will be controlled by ISP COntriller Table of content
Size
A3
Document Number
W0 6N Rev
SA
Date: Saturday, February 19, 2005 Sheet 2 of 44
0 R0603 0 R0603 0 R0603
3D3V_S0 +/-5% 3D3V_S0 +/-5% 3D3V_S0 +/-5%
R93 R521 R77
3D3V_APWR_S0 3D3V_48MPWR_S0 3D3V_CLKGEN_S0
C101 C93 C415 C90 C97 C94 C83 C78 C95 C81 C92 C91
* 4.7uF
* 0.1uF
16V, Y5V, +80%/-20% * 4.7uF
* 0.1uF
16V, Y5V, +80%/-20% * 10uF
6.3V, X5R, +/-10% * 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
* 0.1uF
C0805 C0402 C0805 C0402 C0805 C0402 C0402 C0402 C0402 C0402 C0402 C0402
10V, Y5V, +80%/-20% 10V, Y5V, +80%/-20%
16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%16V, Y5V, +80%/-20%
3D3V_S0
R41
10K
+/-5%
U3 R0402
ITP_EN 0=PCIEX_6 1=CPU_2_ITP
DUMMY
SS_SEL 0=LCDCLK 1=PCIEX/free running 3D3V_APWR_S0 37 54
VDDA CPU_STP# PM_STPCPU# 19
3D3V_S0
3.3V PCI clock output
3D3V_CLKGEN_S0 1 44 RN13 1 4 4P2R0402V CLK_CPU_BCLK 4
VDDPCI CPUT0 33
7 VDDPCI CPUC0 43 2 3 +/-5% CLK_CPU_BCLK# 4
3D3V_S0
21 41 RN15 1 4 4P2R0402V CLK_MCH_BCLK 6
R38 VDDPCIEX CPUT1 33
28 VDDPCIEX CPUC1 40 2 3 +/-5% CLK_MCH_BCLK# 6
R30 R519 10K 34
10K 10K 3D3V_S0 R0402 VDDPCIEX CLK_XDP_CPU 1 TP8
CPUT2_ITP/PCIEXT6 36
+/-5% +/-5% +/-5% 42 35 CLK_XDP_CPU#1 TP9
R0402 R0402 DUMMY VDDCPU CPUC2_ITP/PCIEXC6
48 VDDREF
DUMMY 17 RN17 2 3 4P2R0402V DREFSSCLK 7
LCDCLK_SS/PCIEX0T 33
R39
3D3V_48MPWR_S0 11 VDD_48 LCDCLK_SS/PCIEX0C 18 1 4 +/-5% DREFSSCLK# 7
ITP_EN
SS_SEL 10K R511 33 R0402 +/-5% 19 RN18 2 3 4P2R0402V
36 PCLK_FWH PCIEXT1 33 CLK_PCIE_NEW 23
R0402 R37 33 R0402 +/-5% 56 20 1 4 +/-5%
R34 R35 +/-5%
29 PCLK_MINI
25 PCLK_PCM R514 33 R0402 +/-5% 3
PCICLK2/REQ_SEL
PCICLK3
** PCIEXC1 CLK_PCIE_NEW# 23
10K 10K DUMMY 33 PCLK_KBC R509 33 R0402 +/-5% 4 22 RN19 2 3 4P2R0402V CLK_MCH_3GPLL 7
PCICLK4 PCIEXT2 33
+/-5% +/-5% 32 CLK33_AUDIODJ R510 33 R0402 +/-5% DUMMY 5
PCICLK5 PCIEXC2 23 1 4 +/-5% CLK_MCH_3GPLL# 7
R0402 R0402 35 PCLK_SIO R512 33 R0402 +/-5% H/L: 100/96MHz
DUMMY 28 PCLK_LAN R36 33 R0402 +/-5% SS_SEL 9 24 RN20 2 3 4P2R0402V CLK_PCIE_PEG 14
SELPCIEX_LCDCLK#/PCICLK_F1 PCIEXT3 33
55 25 1 4 +/-5%
19 PM_STPPCI#
19 CLK_ICHPCI R33 33R0402 +/-5% ITP_EN 8
PCI/SRC_STP#
ITP_EN/PCICLK_F0
** PCIEXC3 CLK_PCIE_PEG# 14
H/L : CPU_ITP/SRC7 26 RN21 2 3 4P2R0402V
R51 SATACLKT 33 SATA_CLKP 18
SATACLKC 27 1 4 +/-5% SATA_CLKN 18
VTT_PWRGD# 10
38 CLKEN# VTT_PWRGD#/PD
30 RN16 2 3 4P2R0402V CLK_PCIE_ICH# 19
PCIEXC4 33
0 R0402 +/-5% 19 CLK48_ICH R518 22R0402 +/-5% FS_A 12 USB_48/FS_A PCIEXT4 31 1 4 +/-5% CLK_PCIE_ICH 19
25 CLK48_CARDBUS R516 22R0402 +/-5%
RN14 1 4 4P2R0402V 14 32 NEWCARD_DET#
7 DREFCLK
33 2 3 +/-5% 15
DOT96T * PEREQ2#/PCIEXC5 33
NEWCARD_DET# 23
7 DREFCLK# DOT96C * PEREQ1#/PCIEXT5
12,21,23 SMBC_ICH 46 SCLK
www.hocnghetructuyen.vn 12 SMBD_ICH 47 SDATA GND 13
*
C66 X2_ICS 49 51 DREFSSCLK R174 0 1D5V_S0
X1_ICS XOUT GND R0603 +/-5% DUMMY
50 XIN GND 45
2
33pF GND 29
X2 FS_C 53
FS_B REF1/FS_C/TEST_SEL
X-14D318MHz 16 FS_B/TEST_MODE GND 2
6
1
C65 * R58 GND DREFCLK R513 0
39 IREF 1D5V_S0
475 R0402 +/-1% 52 38 R0603 +/-5% DUMMY
REF0 GNDA
33pF R46 47R0402 +/-5%
19 CLK_ICH14
ICS954226
35 SIO_14M R49 47R0402 +/-5%
*internal Pull-Up resistors
**internal Pull-Down resistor EMI capacitor
R517 CLK_ICH14 C80 10pF C0402 50V, NPO, +/-5% DUMMY
*********
0
CFG1 FS_B CLK33_AUDIODJ C405 10pF C0402 50V, NPO, +/-5% DUMMY
+/-5% R0402 PCLK_PCM C413 10pF C0402 50V, NPO, +/-5% DUMMY
PCLK_MINI C77 10pF C0402 50V, NPO, +/-5% DUMMY
PCLK_KBC C404 10pF C0402 50V, NPO, +/-5% DUMMY
3D3V_CLKGEN_S0
CLK_ICHPCI C64 10pF C0402 50V, NPO, +/-5% DUMMY
CLK48_ICH C414 10pF C0402 50V, NPO, +/-5% DUMMY
R515
PCLK_SIO C411 10pF C0402 50V, NPO, +/-5% DUMMY
1K CLK_PCIE_ICH R59 49.9 R0402 +/-1% CLK_CPU_BCLK R52 49.9 R0402 +/-1%
+/-5% SIO_14M C82 10pF C0402 50V, NPO, +/-5% DUMMY
CLK_PCIE_ICH# R60 49.9 R0402 +/-1% CLK_CPU_BCLK# R54 49.9 R0402 +/-1%
R0402
FS_A DREFSSCLK# R62 49.9 R0402 +/-1% CLK_MCH_BCLK R56 49.9 R0402 +/-1%
FS_C DREFSSCLK R61 49.9 R0402 +/-1% CLK_MCH_BCLK# R57 49.9 R0402 +/-1%
CFG1 CLK_PCIE_NEW R63 49.9 R0402 +/-1% CLK_PCIE_PEG R67 49.9 R0402 +/-1%
CFG1 7
R42 CLK_PCIE_NEW# R64 49.9 R0402 +/-1% CLK_PCIE_PEG# R68 49.9 R0402 +/-1%
FS_C FS_B FS_A CPU
1K DREFCLK R53 49.9 R0402 +/-1% CLK_MCH_3GPLL R66 49.9 R0402 +/-1%
+/-5% 0 0 0 266M
0 0 1 133M (Default) DREFCLK# R55 49.9 R0402 +/-1% CLK_MCH_3GPLL# R65 49.9 R0402 +/-1%
R0402 0 1 0 200M
0
1
1
0
1
0
166M
333M
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