Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop Lenovo 3000 G555 (Compal LA-5972P NAWA2) laptop schematics
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ZZZ1 ZZZ3 ZZZ4 ZZZ5
LA5972P_LS5971P_LS5083P LA5972P LS5971P LS5083P
DAZ@ DAZ@ DAZ@
1 1
Compal Confidential
2 2
NAWA2 Schematics Document
AMD Tigris: Caspian Processor with RS880M/SB710/Park-S3 & M93-S3
3
2009-11-26 3
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 1 of 49
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Compal Confidential
VRAM 512MB
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Tigris
AMD S1G3 Processor
Model Name : NAWA1 Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
64M16 x 4 Fan Control uPGA-638 Package
page 19 page 37 Dual Channel BANK 0, 1, 2, 3 page 8,9
Caspian page 4,5,6,7 1.8V DDRII 667 (800)
1
DDR3 800MHz 1
Hyper Transport Link 5 in 1 socket
LCD (LED BL) ATI PARK-S3 & M93-S3 16 x 16 page 29
uFCBGA-631 PCI-Express 16x
page 21
Page 14,15,16,17,18
Gen2 Thermal Sensor Clock Generator
ATI RS880M Card Reader
CRT ADM1032 SLG8SP626VTR
WINBOND page 6 page 20 RTS5138
page 22
uFCBGA-528 page 29
PCI-Express 1x
page 10,11,12,13 page 32 page 32 page 31 page 32 page 31
USB CMOS Bluetooth USB Mini
MINI Card x1 LAN(10/100)/1000 A link Express2 conn conn card
Camera Conn
WLAN AR8131/AR8132 X2 X1 (WL)X1
page 31 page 30 USB port 0,1 USB port 7 USB port 8 USB port 3 USB port 5 USB port 2
port 2 port 3
2
ATI SB710 3.3V 48MHz USB
2
RJ45 3.3V 24.576MHz/48Mhz HD Audio
page 30 uFCBGA-528
page 23,24,25,26,27 S-ATA
HDA Codec MIC
CX20671 36
page page 36
LPC BUS SATA HDD CDROM
Conn. page 28 Conn. 28
page
port 0 port 1 Phone Jack x2
page 36
ENE KB926
3 page 33 3
Touch Pad Int.KBD
page 34 page 34
Power Board
BIOS
page 35
page 34
DC/DC Interface.
page 38
Power Circuit
4
page 39,40,41,42,43, 4
44,45,46,47,48
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 2 of 49
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Voltage Rails
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BTO Option Table
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
BTO Item BOM Structure
VIN Adapter power supply (19V) N/A N/A N/A Discrete VGA@ Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A PARK PARK@ S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE_0 Core voltage for CPU (0.7-1.2V) ON OFF OFF M93 M93@
+CPU_CORE_1 Core voltage for CPU (0.7-1.2V) ON OFF OFF HDT debug HDT@ S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1
+CPU_CORE_NB Voltage for On-die Northbridge of CPU(0.8-1.1V) ON OFF OFF UMA UMA@ S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF 1
OFF OFF
+0.9V 0.9V switched power rail for DDR terminator ON ON OFF Wireless LAN WLAN@
+1.1VS 1.1V switched power rail for NB VDDC & VGA ON OFF OFF Blue Tooth BT@ S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.2V_HT 1.2V switched power rail ON OFF OFF Camera CMOS@
+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF New Card New Card@
NAWA1_UMA : UMA@/WLAN@/BT@/CMOS@/NEW CARD@
+1.5VS 1.5V power rail for PCIE Card ON OFF OFF VRAM X76@
NAWA1_DIS : VGA@/M93@/WLAN@/BT@/NEW CARD@/CMOS@/X76@
+1.8V 1.8V power rail for CPU VDDIO and DDR ON ON OFF UNPON @
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5VS 2.5V for CPU_VDDA ON OFF OFF
PARK-S3 power on sequence
+3VALW 3.3V always on power rail ON ON ON*
+3V_LAN 3.3V power rail for LAN ON ON ON
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
+3VS_VGA
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON* +VGA_CPRE
+RTCVCC RTC power ON ON ON
+1.1VS_VGA
2 2
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+1.8VS_VGA
External PCI Devices RS880M power on sequence
Device IDSEL# REQ#/GNT# Interrupts
+3VS
(AVDD, VDD33)
+1.8VS
+1.1VS PLL Rails
(PLLVDD, IOPLLVDD)
+NB_CORE
EC SM Bus1 address EC SM Bus2 address
3 3
Device Address HEX Device Address HEX
Smart Battery 0001 011X b 16H ADI ADM1032 (CPU) 1001 100X b 98H
GMT G781-1 (GPU) 1001 101X b 9AH
SB-Temp Sensor 9CH
SB710 SB710
SM Bus 0 address SM Bus 1 address
Device Address HEX Device Address
New card
Clock Generator 1101 001Xb D2
(SILEGO SLG8SP626)
DDR DIMM1 1001 000Xb 90
DDR DIMM2 1001 010Xb 94
Mini card
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 3 of 49
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1 1
+1.2V_HT
VLDT CAP.
250 mil
1 1 1 1 1 1 1
C755 C727 C666 C725 C726 C722 C668
H_CADIP[0..15] H_CADOP[0..15] 10U_0805_6.3V4Z 10U_0805_6.3V4Z 10U_0805_6.3V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 180P_0402_50V8J 180P_0402_50V8J
(10) H_CADIP[0..15] H_CADOP[0..15] (10)
H_CADIN[0..15] H_CADON[0..15] 2 2 2 2 2 2 2
(10) H_CADIN[0..15] H_CADON[0..15] (10)
Near CPU Socket
+1.2V_HT +1.2V_HT
JCPU1A
2 2
D1 VLDT_A0 HT LINK VLDT_B0 AE2 1 2
C664 10U_0805_6.3V4Z
VLDT=1.5A D2
D3
VLDT_A1 VLDT_B1
AE3
AE4
VLDT_A2 VLDT_B2
D4 VLDT_A3 VLDT_B3 AE5
H_CADIP0 E3 AD1 H_CADOP0
H_CADIN0 L0_CADIN_H0 L0_CADOUT_H0 H_CADON0
E2 L0_CADIN_L0 L0_CADOUT_L0 AC1
H_CADIP1 E1 AC2 H_CADOP1
H_CADIN1 L0_CADIN_H1 L0_CADOUT_H1 H_CADON1
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3
H_CADIP2 G3 AB1 H_CADOP2
H_CADIN2 L0_CADIN_H2 L0_CADOUT_H2 H_CADON2
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1
H_CADIP3 G1 AA2 H_CADOP3
H_CADIN3 L0_CADIN_H3 L0_CADOUT_H3 H_CADON3
H1 L0_CADIN_L3 L0_CADOUT_L3 AA3
H_CADIP4 J1 W2 H_CADOP4
H_CADIN4 L0_CADIN_H4 L0_CADOUT_H4 H_CADON4
K1 W3
H_CADIP5 L0_CADIN_L4 L0_CADOUT_L4 H_CADOP5
L3 V1
H_CADIN5 L0_CADIN_H5 L0_CADOUT_H5 H_CADON5
L2 U1
H_CADIP6 L0_CADIN_L5 L0_CADOUT_L5 H_CADOP6
L1 U2
H_CADIN6 L0_CADIN_H6 L0_CADOUT_H6 H_CADON6
M1 U3
H_CADIP7 L0_CADIN_L6 L0_CADOUT_L6 H_CADOP7
N3 L0_CADIN_H7 L0_CADOUT_H7 T1
H_CADIN7 N2 R1 H_CADON7
H_CADIP8 L0_CADIN_L7 L0_CADOUT_L7 H_CADOP8
E5 AD4
H_CADIN8 L0_CADIN_H8 L0_CADOUT_H8 H_CADON8
F5 AD3
H_CADIP9 L0_CADIN_L8 L0_CADOUT_L8 H_CADOP9
F3 AD5
H_CADIN9 L0_CADIN_H9 L0_CADOUT_H9 H_CADON9
F4 AC5
H_CADIP10 L0_CADIN_L9 L0_CADOUT_L9 H_CADOP10
G5 AB4
H_CADIN10 L0_CADIN_H10 L0_CADOUT_H10 H_CADON10
H5 L0_CADIN_L10 L0_CADOUT_L10 AB3
H_CADIP11 H3 AB5 H_CADOP11
H_CADIN11 L0_CADIN_H11 L0_CADOUT_H11 H_CADON11
H4 AA5
H_CADIP12 L0_CADIN_L11 L0_CADOUT_L11 H_CADOP12
K3 Y5
H_CADIN12 L0_CADIN_H12 L0_CADOUT_H12 H_CADON12
K4 W5
H_CADIP13 L0_CADIN_L12 L0_CADOUT_L12 H_CADOP13
L5 V4
3 H_CADIN13 L0_CADIN_H13 L0_CADOUT_H13 H_CADON13 3
M5 L0_CADIN_L13 L0_CADOUT_L13 V3
H_CADIP14 M3 V5 H_CADOP14
H_CADIN14 L0_CADIN_H14 L0_CADOUT_H14 H_CADON14
M4 U5
H_CADIP15 L0_CADIN_L14 L0_CADOUT_L14 H_CADOP15
N5 L0_CADIN_H15 L0_CADOUT_H15 T4
H_CADIN15 P5 T3 H_CADON15
L0_CADIN_L15 L0_CADOUT_L15
(10) H_CLKIP0 J3 Y1 H_CLKOP0 (10)
L0_CLKIN_H0 L0_CLKOUT_H0
(10) H_CLKIN0 J2 W1 H_CLKON0 (10)
L0_CLKIN_L0 L0_CLKOUT_L0
(10) H_CLKIP1 J5 Y4 H_CLKOP1 (10)
L0_CLKIN_H1 L0_CLKOUT_H1
(10) H_CLKIN1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 H_CLKON1 (10)
(10) H_CTLIP0 N1 R2 H_CTLOP0 (10)
L0_CTLIN_H0 L0_CTLOUT_H0
(10) H_CTLIN0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 H_CTLON0 (10)
(10) H_CTLIP1 P3 T5 H_CTLOP1 (10)
L0_CTLIN_H1 L0_CTLOUT_H1
(10) H_CTLIN1 P4 L0_CTLIN_L1 L0_CTLOUT_L1 R5 H_CTLON1 (10)
6090022100G_B ME@
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/10/06 Deciphered Date 2009/10/06 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AMD CPU S1G3 HT I/F
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-5972P
Date: Thursday, December 10, 2009 Sheet 4 of 49
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PLACE CLOSE TO PROCESSOR
Processor DDR2 Memory Interface
WITHIN 1.2 INCH
JCPU1C
(9) DDRB_SDQ[63..0]
MEM:DATA
DDRA_SDQ[63..0] (8)
DDRA_CLK0 DDRB_SDQ0 C11 G12 DDRA_SDQ0
1 +1.8V DDRB_SDQ1 MB_DATA0 MA_DATA0 DDRA_SDQ1 1
1 A11 MB_DATA1 MA_DATA1 F12
DDRB_SDQ2 A14 H14 DDRA_SDQ2
C888 DDRB_SDQ3 MB_DATA2 MA_DATA2 DDRA_SDQ3
B14 MB_DATA3 MA_DATA3 G14
2
1.5P_0402_50V9C DDRB_SDQ4 G11 H11 DDRA_SDQ4
R78 DDRA_CLK0# 2 DDRB_SDQ5 MB_DATA4 MA_DATA4 DDRA_SDQ5
E11 H12
1K_0402_1% DDRB_SDQ6 MB_DATA5 MA_DATA5 DDRA_SDQ6
D12 MB_DATA6 MA_DATA6 C13
DDRA_CLK1 DDRB_SDQ7 A13 E13 DDRA_SDQ7
DDRB_SDQ8 MB_DATA7 MA_DATA7 DDRA_SDQ8
1 A15 H15
1
+MCH_REF DDRB_SDQ9 MB_DATA8 MA_DATA8 DDRA_SDQ9
A16 MB_DATA9 MA_DATA9 E15
1000P_0402_25V8J
0.1U_0402_16V4Z
C891 DDRB_SDQ10 A19 E17 DDRA_SDQ10
MB_DATA10 MA_DATA10
2
1 1 1.5P_0402_50V9C DDRB_SDQ11 A20 H17 DDRA_SDQ11
2 MB_DATA11 MA_DATA11
C178
C177
R79 DDRA_CLK1# DDRB_SDQ12 C14 E14 DDRA_SDQ12
1K_0402_1% DDRB_SDQ13 MB_DATA12 MA_DATA12 DDRA_SDQ13
D14 MB_DATA13 MA_DATA13 F14
DDRB_SDQ14 C18 C17 DDRA_SDQ14
2 2 DDRB_CLK0 DDRB_SDQ15 MB_DATA14 MA_DATA14 DDRA_SDQ15
D18 G17
1
DDRB_SDQ16 MB_DATA15 MA_DATA15 DDRA_SDQ16
1 D20 G18
DDRB_SDQ17 MB_DATA16 MA_DATA16 DDRA_SDQ17
A21 MB_DATA17 MA_DATA17 C19
C890 DDRB_SDQ18 D24 D22 DDRA_SDQ18
1.5P_0402_50V9C DDRB_SDQ19 MB_DATA18 MA_DATA18 DDRA_SDQ19
C25 MB_DATA19 MA_DATA19 E20
DDRB_CLK0# 2 DDRB_SDQ20 B20 E18 DDRA_SDQ20
DDRB_SDQ21 MB_DATA20 MA_DATA20 DDRA_SDQ21
C20 F18
DDRB_CLK1 DDRB_SDQ22 MB_DATA21 MA_DATA21 DDRA_SDQ22
B24 B22
DDRB_SDQ23 MB_DATA22 MA_DATA22 DDRA_SDQ23
1 C24 MB_DATA23 MA_DATA23 C23
DDRB_SDQ24 E23 F20 DDRA_SDQ24
C889 DDRB_SDQ25 MB_DATA24 MA_DATA24 DDRA_SDQ25
E24 F22
1.5P_0402_50V9C DDRB_SDQ26 MB_DATA25 MA_DATA25 DDRA_SDQ26
G25 MB_DATA26 MA_DATA26 H24
DDRB_CLK1# 2 DDRB_SDQ27 G26 J19 DDRA_SDQ27
DDRB_SDQ28 MB_DATA27 MA_DATA27 DDRA_SDQ28
C26 E21
DDRB_SDQ29 MB_DATA28 MA_DATA28 DDRA_SDQ29
D26 MB_DATA29 MA_DATA29 E22
DDRB_SDQ30 G23 H20 DDRA_SDQ30
+0.9V +0.9V DDRB_SDQ31 MB_DATA30 MA_DATA30 DDRA_SDQ31
G24 H22
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