Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop Lenovo G470 drawings G570 drawing LA-6758P
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A B C D E
1 1
2
Compal Confidential 2
G470/G570 DIS+UMA+Muxless M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
ATI Robson/PX3.0,PX4.0
3
2010-07-22 3
LA-6758P
REV:0.1
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6758P
Date: Tuesday, August 17, 2010 Sheet 1 of 57
A B C D E
A B C D E
Compal confidential For 14"(Page 4x) For 15"(Page 4x+1)
File Name : G470/G570 LS6753P PWR/B LS6753P PWR/B
LS6751P CardReader/B LS6751P CardReader/B
Page23-30 LS6754P LED/B
AMD LS6755P ODD/B
Intel
1
Robson XT Sandy Bridge 1
VRAM 64*16 PCI-E x16 DDR3 SO-DIMM *2
DDR3*4 Socket-rPGA988B BANK 0, 1, 2, 3 Page12-13
37.5mm*37.5mm
Dual Channel Up to 8GB
HDMI Page33 Page5-11 DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
Connector
100MHz
Page32 2.7GT/s FDI *8 DMI *4
CRT
Connector Audio Codec 2 channel speaker
Intel
AZALIA Conexant
LVDS Page31 Cougar Point CX20671
Int. MIC
2 Connector FCBGA 989 2
Audio Jacks
25mm*25mm Page39
LAN Page35 PCI-E x1 *6 USB2.0 *14
Athros Camera Conn.
AR8151-B(GLAN)
AR8152-B(10/100) SATA *6 BlueTooth Conn.
Page42
Page14-22
RJ-45 Page36
SPIROM Mini Card Slot *1
Page34
Connector BIOS
LPC BUS Card Reader
PCI Express PCI-E(WLAN)
Page40 Reltek
Mini Card Slot *1
EC RTS5139
3 USB(WiMAX) ENE KB930 SDXC/MMC/MS/xD 3
WLAN ENE KB9012
WiMAX Page34 USB2.0 *1(Right)
USB2.0 *2(Left)
Touch Pad Int. KBD
Thermal Sensor SPI ROM
Page41
eSATA+USB(Left) Page42
EMC1403 Page37
SATA3 HDD (Port 0/Port 1 support SATA3)
Page38
SATA ODD Page38
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6758P
Date: Tuesday, August 17, 2010 Sheet 2 of 57
A B C D E
A B C D E
SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
+5VS S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+3VS
power S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
plane +1.5VS
1
+VCCP S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+5VALW +1.5V +CPU_CORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+B +VGA_CORE
+3VALW +GFX_CORE
+1.8VS BOARD ID Table Board ID / SKU ID Table for AD channel
State +0.75VS Vcc 3.3V +/- 5%
+1.05VS
Board ID PCB Revision
Ra/Rc/Re 100K +/- 5%
0 0.1 Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
1
0 0 0 V 0 V 0 V EVT
2
1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V DVT
3
2 18K +/- 5% 0.436 V 0.503 V 0.538 V PVT
4
3 33K +/- 5% 0.712 V 0.819 V 0.875 V MP
S0
5
O O O O 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
6
5 100K +/- 5% 1.453 V 1.650 V 1.759 V
7
6 200K +/- 5% 1.935 V 2.200 V 2.341 V
S3 7 NC 2.500 V 3.300 V 3.300 V
O O O X
2 2
S5 S4/AC
O O X X
USB Port Table BOM Structure Table
S5 S4/ Battery only
O X X X 3 External BTO Item BOM Structure
USB 2.0 USB 1.1 Port USB Port
S5 S4/AC & Battery
UMA only PX@
don't exist X X X X 0 USB/B (Right Side) Muxless PX@+VGA@
UHCI0
Address 1 USB Port (Left Side) Discrete Only DIS@+VGA@
EC SM Bus1 address EC SM Bus2 address 2 USB Port (Left Side) PX3.0 only, not for BACO PX3@
UHCI1
3 USB Port (Left Side) BACO BACO@
Device Device Address EHCI1
4 COMMON HDMI HDMI@
Smart Battery 0001 011X b Thermal Sensor EMC1403-2 1001_101xb UHCI2
Thermal Sensor EMC1402-1 100_1100 b
5 Camera UMA HDMI UMA_HDMI@
6 Discrete HDMI VGA_HDMI@
UHCI3
7 eSATA ESATA@
PCH SM Bus address 8 Mini Card(WLAN) Blue Tooth BT@
UHCI4
9 Connector ME@
Device Address
DDR DIMM0
10 45 LEVEL 45@
3
1001 000Xb EHCI2 UHCI5 3
DDR DIMM2 1001 010Xb
11 Card Reader 10/100 LAN 8152@
12 GIGA LAN GIGA@
UHCI6
13 Blue Tooth Cameara CMOS@
SMBUS Control Table
Unpop @
Thermal
WLAN Sensor
SOURCE VGA BATT KE930 SODIMM WWAN PCH
SMB_EC_CK1
SMB_EC_DA1
KB930 X V
+3VALW
X X X X X
+3VALW
SMB_EC_CK2
SMB_EC_DA2
KB930 X X X X X X V
+3VS
+3VALW
SMBCLK
SMBDATA
PCH X X X V
+3VS
V
+3VS
X X
+3VALW
SML0CLK
SML0DATA
PCH X X X X X X X
+3VALW
4 4
SML1CLK
SML1DATA
PCH
+3VALW +3VS
V X V
+3VS
X X V
+3VS
X
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6758P
Date: Tuesday, August 17, 2010 Sheet 3 of 57
A B C D E
5 4 3 2 1
Without BACO option :
Power-Up/Down Sequence PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
sequence, though a shorter ramp-up duration is preferred.
BACO option :
2. VDDR3 should ramp-up before or simultaneously with VDDC. PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
D DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10. dGPU Power Pins Voltage PX 3.0 BACO Mode Max current
D
4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, 1.8V OFF ON 1679mA
VDD_CT have ramped up. DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
DPLL_PVDD, MPV18, and SPV18
ramp-up (or vice versa).)
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and 1.0V OFF ON 575mA
SPV10
PCIE_VDDC 1.0V OFF ON 2A
VDDR3(3.3VGS) Note: Do not drive any IOs before VDDR3 is ramped up.
VDDR3 , and A2VDD 3.3V OFF ON 190mA
BIF_VDDC (current consumption = [email protected], in Same as OFF ON 70mA
PCIE_VDDC(1.0V) BACO mode) VDDC Same as
PCIE_VDDC
VDDR1 1.5V OFF OFF 2.8A
C
VDDR1(1.5VGS) VDDC/VDDCI 1.12V OFF OFF 12.9A C
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
PE_GPIO0 PE_EN BACO Switch
iGPU dGPU
PERSTb BIF_VDDC
PE_GPIO1
REFCLK PX_mode
B +3.3VALW MOS
+3.3VGS B
Straps Reset 1
+1.5V SI4800
+1.5VGS
Straps Valid +1.0V +1.0VGS
Regulator
2 3
Global ASIC Reset
+B Regulator
+VGA_CORE
+1.8V +1.8VGS
T4+16clock
SI4800
5 4
PWRGOOD
A A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/07/12 Deciphered Date 2012/07/11 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
dGPU Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Document Number Rev
B 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-6758P
Date: Tuesday, August 17, 2010 Sheet 4 of 57
5 4 3 2 1
5 4 3 2 1
D D
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
+1.05VS impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
1
max length = 500 mils
R1
24.9_0402_1%
- typical impedance = 14.5 mohms
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI
J21
PEG_ICOMPO
[16] DMI_CRX_PTX_N0 B27 H22
DMI_RX#[0] PEG_RCOMPO
[16] DMI_CRX_PTX_N1 B25 DMI_RX#[1]
[16] DMI_CRX_PTX_N2 A25 PCIE_CRX_GTX_N[0..15] [23]
DMI_RX#[2] PCIE_CRX_GTX_N15
[16] DMI_CRX_PTX_N3 B24 DMI_RX#[3] PEG_RX#[0] K33
M35 PCIE_CRX_GTX_N14
PEG_RX#[1] PCIE_CRX_GTX_N13
[16] DMI_CRX_PTX_P0 B28 L34
DMI_RX[0] PEG_RX#[2] PCIE_CRX_GTX_N12
[16] DMI_CRX_PTX_P1 B26
DMI_RX[1] PEG_RX#[3]
J35 PEG Static Lane Reversal - CFG2 is for the 16x
DMI
A24 J32 PCIE_CRX_GTX_N11
[16] DMI_CRX_PTX_P2 DMI_RX[2] PEG_RX#[4]
B23 H34 PCIE_CRX_GTX_N10
[16] DMI_CRX_PTX_P3 DMI_RX[3] PEG_RX#[5]
H31 PCIE_CRX_GTX_N9 1: Normal Operation; Lane # definition matches
PEG_RX#[6] PCIE_CRX_GTX_N8
[16] DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33 CFG2 socket pin map definition
E22 G30 PCIE_CRX_GTX_N7
[16] DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8] PCIE_CRX_GTX_N6
[16] DMI_CTX_PRX_N2 F21 F35
DMI_TX#[2] PEG_RX#[9] PCIE_CRX_GTX_N5
D21 E34 0:Lane Reversed
[16]
[16]
DMI_CTX_PRX_N3
DMI_CTX_PRX_P0 G22
DMI_TX#[3]
DMI_TX[0]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
E32
D33
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3 *
D22 D31 PCIE_CRX_GTX_N2
C [16] DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PCIE_CRX_GTX_N1 C
PCI EXPRESS* - GRAPHICS
[16] DMI_CTX_PRX_P2 F20 DMI_TX[2] PEG_RX#[14] B33
C21 C32 PCIE_CRX_GTX_N0
[16] DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
PCIE_CRX_GTX_P[0..15] [23]
J33 PCIE_CRX_GTX_P15
PEG_RX[0] PCIE_CRX_GTX_P14
PEG_RX[1] L35
K34 PCIE_CRX_GTX_P13
PEG_RX[2] PCIE_CRX_GTX_P12
[16] FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PCIE_CRX_GTX_P11
[16] FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4] PCIE_CRX_GTX_P10
[16] FDI_CTX_PRX_N2 E19 FDI0_TX#[2] PEG_RX[5] G34
F18 G31 PCIE_CRX_GTX_P9
Intel(R) FDI
[16] FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6] PCIE_CRX_GTX_P8
DISCRETE ONLY [16] FDI_CTX_PRX_N4 B21 FDI1_TX#[0] PEG_RX[7] F33
C20 F30 PCIE_CRX_GTX_P7
[16] FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
1K_0402_5% 2 DIS@ 1 R2 FDI_FSYNC0 D18 E35 PCIE_CRX_GTX_P6
[16] FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9] PCIE_CRX_GTX_P5
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