Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop Lenovo Ideapad Y430 (Compal LA-4141p) laptop schematics
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A B C D E
1 1
2
JITR1/R2_DDR3 2
Schematics Document
Mobile Penryn uFCPGA with Intel
3
Cantiga_GM/PM+ICH9-M core logic 3
Friday, April 18, 2008
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JITR1_LA-4141P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 1 of 52
A B C D E
A B C D E
ZZZ2
Compal confidential
File Name : POWER Board CAP SENSE LEDs Board CONTROL Board
14W_PCB_LA4142P
MODEM_CX20548
VRAM 16*16 Mobile Penryn MDC board
1 VRAM 32*16 uFCPGA-478 CPU
1
page20,21
PCI-E X16 Clock Gen.
nVIDIA NB9M page5,6,7 SLG8SP556VTR
ICS9LPRS387AKLFT
page16,19 page22
H_A#(3..35)
FSB
H_D#(0..63) 667/800/1066MHz
HDMI CH7318 PCI-E DDR2 -667 (1.8V)
CONN DDR2-SO-DIMM X2
page23
page23
Intel Cantiga GMCH DDR2 -800 (1.8V) BANK 0, 1, 2, 3 page 14,15
CRT & TV OUT PCBGA 1329 Dual Channel
LVDS I/F
page25
page 8,9,10,11,12,13
2 2
LVDS
Connector page24 DMI C-Line
AMP&Audio Jack
AZALIA page24
PCI Express 6*PCI-E BUS 12*USB2.0
Mini card Slotpage32
1 Intel ICH9-M Audio Codec
mBGA-676 AMOM_CX20561
page30
PCI Express 3.3V / 33 MHz
PCI BUS
Mini card Slotpage32
2 New Card 4*SATA serial
page40 page26,27,28,29
BCM5906 1394+Card Reader CMOS Camera
10/100/LAN page33 O2 OZ129T LPC BUS page40
page36
3 3
BlueTooth Conn
page32
RJ45 CONN 1394 Conn EC
page34 USB conn X3
page36 ENE KB926 page43
page35
Card reader(XD/SD
MMC/MS/MS-Pro Int.KBD
HD SD) page36 page37
SUB Board page32,36 SATA HDD
BIOS page38
Connector page39
*RJ45 CONN Touch Pad
*1394 CONN
*RJ11 CONN page37
SATA CDROM
*DC JACK
*MIC IN JACK
*HP OUT JACK
*USB CONN Connector page39
*SWITCH
4
*LED 4
*SWITCH
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
MB Block Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom JITR1_LA-4141P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 09, 2008 Sheet 2 of 52
A B C D E
A B C D E
DDR2 Voltage Rails
+5VS
+3VS SMBUS, SPI and I2C Control Table
+1.5VS
1
power 1
plane +0.9VS SERIAL NEW CLK CAP Mini Mini THERMAL THERMAL
SOURCE HDMI LVDS CRT HDCP EEPROM BATT SENSOR SENSOR
+VCCP CARD GEN sensor CARD1 CARD2 (VGA) (CPU)
+5VALW +1.8V +CPU_CORE
+B +VGA_CORE
EC_SMB_CK1
EC_SMB_DA1
KB926 X X X X V X X X X X V V X
+3VALW +1.8VS
EC_SMB_CK2
EC_SMB_DA2
KB926 X X X X X X X V X X X V V
State
ICH_SMBCLK
ICH_SMBDAT ICH9 X X X X X V V X V V X X X
LVDS_SCL
LVDS_SDA Cantiga
X V X X X X X X X X X X X
GMCH_CRT_CLK
S0
O O O O GMCH_CRT_DAT Cantiga
X X V X X X X X X X X X X
HDMICLK_NB
S1
O O O O HDMIDAT_NB Cantiga
V X X X X X X X X X X X X
2
S3
O O O X
VGA_DDCCLK
VGA_DDCDATA VGA X X V X X X X X X X X X X 2
S5 S4/AC
O O X X
VGA_LVDS_SCL
VGA_LVDS_DAT VGA X V X X X X X X X X X X X
VGA_HDMI_SCL
S5 S4/ Battery only
O X X X VGA_HDMI_DAT VGA
V X X X X X X X X X X X X
S5 S4/AC & Battery
X X X X
HDCP_SMB_CK1
HDCP_SMB_DA1 VGA X X X X V X X X X X X X X
don't exist
FSEL#SPICS#_SB
FRD#SPI_SO_SB
SPI_CLK_SB
FWR#SPI_SI_SB
ICH9 X X X X V X X X X X X X X
DDR3 Voltage Rails
FSEL#SPICS#
+5VS
FRD#SPI_SO
SPI_CLK
FWR#SPI_SI
KB926 X X X X V X X X X X X X X
+3VS
+1.5VS
power
plane +0.75V
3 3
+VCCP
+5VALW +1.5V +CPU_CORE
+B +VGA_CORE
+3VALW +1.8VS
State
S0
O O O O
S1
O O O O
S3
4
O O O X 4
S5 S4/AC
O O X X
S5 S4/ Battery only
O X X X Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
S5 S4/AC & Battery MB Notes List
don't exist X X X X THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B JITR1_LA-4141P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 09, 2008 Sheet 3 of 52
A B C D E
A B C D E
VGA and DDR2 Voltage Rails (NB9M-GS) EDP at Tj = 97C*
Power Supply Rail NB9M-GS NB9M-GE
(V) GDDR3 DDR2 GDDR3 DDR2
NVVDD Variable 11.22A 10.87A 9.2A 8.88A
FB_DLLAVDD 1.1 25mA
power FB_PLLAVDD 1.1 10mA
plane +3VS IFPC_IOVDD 1.1 385mA
1 1
+1.8V +VGA_CORE IFPD_IOVDD 1.1 385mA
IFPE_IOVDD 1.1 385mA
IFPF_IOVDD 1.1 385mA
PEX_IOVDD/Q 1.1 1550mA
PEX_PLLVDD 1.1 165mA
State
PLLVDD 1.1 55mA
SP_PLLVDD 1.1 25mA
VID_PLLVDD 1.1 50mA
TOTAL 1.1 3.425A
FBVDD/Q 1.8 2.24A 1.65A 2.17A 1.63A
S0 IFPA_IOVDD 1.8 50mA
O O O O
IFPB_IOVDD 1.8 50mA
S1 IFPAB_PLLVDD 1.8 100mA
O O O O
IFPCD_PLLVDD 1.8 160mA
S3 IFPEF_PLLVDD 1.8 160mA
2
O O O X 2
TOTAL 1.8 2.76A 2.17A 2.69A 2.15A
S5 S4/AC
O O X X DACA_VDD 3.3 110mA
DACB_VDD 3.3 125mA
S5 S4/ Battery only
O X X X DACC_VDD 3.3 110mA
MIOA_VDDQ 3.3 10mA
S5 S4/AC & Battery
don't exist X X X X MIOB_VDDQ 3.3 10mA
VDD33 3.3 80mA
TOTAL 3.3 0.445A
POWER SQUENCE
The ramp time for any rail must be more than 40us
3 3
(+3VS) VDD33
PEX_VDD can ramp up any time
(1.1VS) PEX_VDD
tNVVDD>=0
(+VGA_CORE) NVVDD
tNV-FB
tFBVDDQ>=0
4
(1.8VS) FBVDDQ 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/10/15 Deciphered Date 2008/10/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B JITR1_LA-4141P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, January 09, 2008 Sheet 4 of 52
A B C D E
5 4 3 2 1
XDP Reserve +3VS
XDP_DBRESET# 1 2 @ 1K_0402_5%
R43
+VCCP
XDP_TDI R11 1 2 54.9_0402_1%
D XDP_TMS R14 1 2 54.9_0402_1% D
CONN@ +VCCP XDP_TDO R12 1 2 54.9_0402_1%
<8> H_A#[3..16]
JCPUA
H_A#3 J4 H1 H_ADS# @
A[3]# ADS# H_ADS# <8>
ADDR GROUP_0
ADDR GROUP_0
H_A#4 L5 E2 H_BNR#
A[4]# BNR# H_BNR# <8>
H_A#5 L4 G5 H_BPRI#
A[5]# BPRI# H_BPRI# <8>
1
H_A#6 K5 R83
H_A#7 A[6]# H_DEFER# 56_0402_5%
M3 A[7]# DEFER# H5 H_DEFER# <8>
H_A#8 N2 F21 H_DRDY# XDP_TRST# R16 1 2 54.9_0402_1%
A[8]# DRDY# H_DRDY# <8>
H_A#9 J1 E1 H_DBSY#
A[9]# DBSY# H_DBSY# <8>
H_A#10 N3 XDP_TCK R15 1 2 54.9_0402_1%
2
H_A#11 A[10]# H_BR0#
P5 A[11]# BR0# F1 H_BR0# <8>
H_A#12 P2 A[12]#
CONTROL
H_A#13 L2 D20 H_IERR#
H_A#14 A[13]# IERR# H_INIT#
P4 A[14]# INIT# B3 H_INIT# <27>
H_A#15 P1
H_A#16 A[15]# H_LOCK#
R1 A[16]# LOCK# H4 H_LOCK# <8>
H_ADSTB#0 M1
<8> H_ADSTB#0 ADSTB[0]#
C1 H_RESET#
RESET# H_RESET# <8>
H_REQ#0 K3 F3 H_RS#0
<8> H_REQ#0 REQ[0]# RS[0]# H_RS#0 <8> +3VS
H_REQ#1 H2 F4 H_RS#1
<8> H_REQ#1 REQ[1]# RS[1]# H_RS#1 <8> +3VS
H_REQ#2 K2 G3 H_RS#2
<8> H_REQ#2 REQ[2]# RS[2]# H_RS#2 <8>
H_REQ#3 J3 G2 H_TRDY#
<8> H_REQ#3 REQ[3]# TRDY# H_TRDY# <8>
2
H_REQ#4 L1
<8> H_REQ#4 REQ[4]# H_HIT# R95
0.1U_0402_16V4Z
<8> H_A#[17..35] HIT# G6 H_HIT# <8> 1
H_A#17 Y2 E4 H_HITM# 10K_0402_5%
A[17]# HITM# H_HITM# <8> C89
H_A#18 U5
H_A#19 A[18]# XDP_BPM#0
R3 AD4
1
A[19]# BPM[0]# 2
ADDR GROUP_1
C H_A#20 W6 AD3 XDP_BPM#1 C
H_A#21 A[20]# BPM[1]# XDP_BPM#2 U5
U4 A[21]# BPM[2]# AD1
H_A#22 Y5 AC4 XDP_BPM#3 1 8 EC_SMB_CK2 EC_SMB_CK2 <16,35,41>
H_A#23 A[22]# BPM[3]# XDP_BPM#4 VDD SCLK
XDP/ITP SIGNALS
U1 A[23]# PRDY# AC2
H_A#24 R4 AC1 XDP_BPM#5 H_THERMDA 2 7 EC_SMB_DA2
A[24]# PREQ# D+ SDATA EC_SMB_DA2 <16,35,41>
H_A#25 T5 AC5 XDP_TCK C95
H_A#26 A[25]# TCK XDP_TDI H_THERMDC
T3 A[26]# TDI AA6 1 2 3 D- ALERT/THERM2 6
H_A#27 W2 AB3 XDP_TDO 2200P_0402_50V7K
H_A#28 A[27]# TDO XDP_TMS THERM#
W5 A[28]# TMS AB5 2200p change to 4 THERM GND 5
H_A#29 Y4 AB6 XDP_TRST# 1000p for ADT7421
H_A#30 A[29]# TRST# XDP_DBRESET# R94
U2 A[30]# DBR# C20 XDP_DBRESET# <28>
H_A#31 V4 +3VS 1 2 S IC EMC1402-1-ACZL-TR MSOP 8P SENSOR
H_A#32 A[31]# 10K_0402_5%
W3 A[32]# 2 1 +VCCP
H_A#33 AA4 THERMAL R84 68_0402_5% Address:100_1100
H_A#34 A[33]# H_PROCHOT#
AB2 A[34]# H_PROCHOT#
H_A#35 AA3 D21
H_ADSTB#1 A[35]# PROCHOT# H_THERMDA
<8> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC
H_A20M# THERMDC
<27> H_A20M# A6 A20M#
ICH
ICH
H_FERR# A5 C7 H_THERMTRIP#
<27> H_FERR# FERR# THERMTRIP# H_THERMTRIP# <8,27>
H_IGNNE# C4
<27> H_IGNNE# IGNNE#
H_STPCLK# D5
<27> H_STPCLK# STPCLK#
H_INTR C6 H CLK
<27> H_INTR
<27> H_NMI
H_NMI
H_SMI#
B4
A3
LINT0
LINT1 BCLK[0] A22
A21
CLK_CPU_BCLK
CLK_CPU_BCLK#
CLK_CPU_BCLK <22> FAN1 Conn
<27> H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# <22>
M4 +5VS +5VS
RSVD[01] C594 10U_0805_10V4Z
B
N5 RSVD[02] H_THERMDA, H_THERMDC routing together, B
T2 RSVD[03] 1 2
1
V3 Trace width / Spacing = 10 / 10 mil
RSVD[04] D17
B2
RESERVED
RSVD[05] U24 @ 1SS355TE-17_SOD323-2
RSVD pins on the CPU D2 RSVD[06] FAN solution RC (R=1Kohm,C=0.1uF)
should be left as NO D22 RSVD[07] 1 VEN GND 8
D3 2 7 D16
2
CONNECT F6
RSVD[08] +VCC_FAN1 3
VIN GND
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