Service Manuals, User Guides, Schematic Diagrams or docs for : LENOVO Laptop Thinkpad X100E (Quanta FL3 Congo) Lenovo+Thinkpad+X100E+(Quanta+FL3+Congo)
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5 4 3 2 1
PCB STACK UP MK-Note Block Diagram -- AMD CONGO
LAYER 1 : TOP
LAYER 2 : SGND
LAYER 3 : IN1
D
LAYER 4 : SVCC
Clock D
LAYER 5 : IN2 Thermal AMD ASB1r2 DDR2 SO-DIMM 1 Gengerator
LAYER 6 : IN3 Sensor Conesus
LAYER 7 : SGND1 27mmX27mm 812pin BGA DDR2 SO-DIMM 2
LAYER 8 : BOT
HT-LINK 16X
LVDS PCI-e/USB WLAN
11.6" HD Mini PCIe Slot Module
NORTH BRIDGE
(1366x768) LCD or PCI-e/USB WWAN
RS780MN A13 Mini PCIe Slot Module
SIM Card
C C
RGB 21mmX21mm, 528pin BGA
CRT PCI-e 10/100/1G
Sideport
Ethernet RJ-45
Memory Realtek
A_LINK 4X RTL8111DL
HP/Mic HDA CODEC HD 2.5" HDD /
Audio SATA
Audio SOUTH BRIDGE SSD Module
B
Jack ALC269VB (Option) B
SB710 A14
Card Reader 4 in 1 Socket
21mmX21mm, 528pin BGA USB
Realtek
Internal Internal SD/MMC/MS/MS-Pro
RTL5159
MIC SPK LPC BUS USB
USB PORT X 3
ITE8502E SPI USB
Camera Conn. Camera Module
Flash
A
USB Bluetooth A
Accelerometer
(BDC-2)
(APS)
Int. KB T/P Battery Charger Quanta Computer Inc.
PROJECT : Congo
Size Document Number Rev
1A
Block Diagram
Date: Thursday, October 22, 2009 Sheet 1 of 42
5 4 3 2 1
5 4 3 2 1
CLK_GEN_SLG8SP628 02
+3V +1.2V +1.2V_CLK_VDDIO
+3V_CLK_VDD
3.3V(250mA) 1.2V(53mA)
L40 BLM18EG601SN1D_6 L27 BLM18AG601SN1D_6
C484 C325 C286 C287 C285 C315 C347 C354 C339 C284 C288 C321 C342 C353
D 22U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 22U/6.3V_8 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 0.1U/10V_4 D
ICS9LPRS480 P/N : ALPRS480000 Clock chip has internal serial terminations
for differencial pairs, external resistors are
SLG8SP628 P/N : AL8SP628000 reserved for debug purpose.
RTM880N-796 P/N : AL000880000
Place within 0.5"
of CLKGEN R186
U18
*261/F_4
4 50 CLK_CPUP_R RP32 1 2 0_4P2R_4
+3V_CLK_VDD VDDDOT CPUK8_0T CLK_CPUP 5
16 49 CLK_CPUN_R 3 4 To CPU Diff 200MHz
VDDSRC CPUK8_0C CLK_CPUN 5
26 VDDATIG
35 VDDSB_SRC
40 30 CLK_NBGFXP_R RP33 1 2 0_4P2R_4
VDDSATA ATIG0T CLK_NBGFXP 8
48 29 CLK_NBGFXN_R 3 4 To NB Diff 100MHz
+3V +3V_CLK_48 VDDCPU ATIG0C CLK_NBGFXN 8
55 VDDHTT ATIG1T 28
L39 BLM18AG601SN1D_6
3.3V(53mA) 56 VDDREF ATIG1C 27
63 VDD48
C483 37 CLK_SBREFP_R RP30 1 2 0_4P2R_4
C SB_SRC0T CLK_SBREFP 8 C
11 36 CLK_SBREFN_R 3 4 To NB Diff 100MHz
+1.2V_CLK_VDDIO VDDSRC_IO0 SB_SRC0C CLK_SBREFN 8
2.2U/6.3V_6 17 32 CLK_SBSRCP_R RP31 1 2 0_4P2R_4
VDDSRC_IO1 SB_SRC1T CLK_SBSRCP 10
25 31 CLK_SBSRCN_R 3 4 To SB Diff 100MHz
VDDATIG_IO SB_SRC1C CLK_SBSRCN 10
34 VDDSB_SRC_IO
47 VDDCPU_IO
22 NBGPP_CLKP_R T61
SRC0T NBGPP_CLKN_R
SRC0C 21 T63
1 20 CLK_PCIE_NEW_R T60
GND48 SRC1T CLK_PCIE_NEW#_R
7 GNDDOT SRC1C 19 T62
10 15 CLK_PCIE_WLANP_R RP37 1 2 0_4P2R_4
GNDSRC0 SRC2T CLK_PCIE_WLANP 23
18 14 CLK_PCIE_WLANN-R 3 4 To Mini PCIE Slot (WLAN)
GNDSRC1 SRC2C CLK_PCIE_WLANN 23
CLK_PCIE_WANP_R RP36 2 0_4P2R_4
24
33
GNDATIG QFN64 SRC3T 13
12 CLK_PCIE_WANN_R
1
3 4
CLK_PCIE_WANP 24
To Mini PCIE Slot (WWAN)
GNDSB_SRC SRC3C CLK_PCIE_WANN 24
43 9 CLK_PCIE_LANP_R RP35 1 2 0_4P2R_4
GNDSATA SRC4T CLK_PCIE_LANP 19
46 8 CLK_PCIE_LANN_R 3 4 To LAN Controller
GNDCPU SRC4C CLK_PCIE_LANN 19
C338 52
CG_XIN GNDHTT
60 GNDREF
SRC6T/SATAT 42 T42
2
33P/50V_4 41 T44
Y4 CG_XIN SRC6C/SATAC
61 X1 SRC7T/27M_SS 6 T64
14.318MHZ CG_XOUT 62 5 T65
C350 X2 SRC7C/27M_NS
1
CG_XOUT
2 54 NBHT_REFCLKP_R RP34 1 2 0_4P2R_4
11,15,27 PCLK_SMB SMBCLK HTT0T/66M HT_REFCLKP 8
33P/50V_4 3 53 NBHT_REFCLKN_R 3 4 To NB Diff 100MHz
11,15,27 PDAT_SMB SMBDAT HTT0C/66M HT_REFCLKN 8
CLK_PD# 51 64 CLK_48M_USB_R R274 22_4 To SB 48MHz
PD# 48MHz_0 CLK_48M_USB 11
R275 *22_4 To RTS5159 48MHz
CLK_48M_USB_CR 22
+3V_CLK_VDD CLKREQ0# SEL_HTT66
EC A57 NB CLOCK INPUT TABLE
T59 23 CLKREQ0# REF0/SEL_HTT66 59
T53 CLKREQ1# 45 58 SEL_SATA R205 33_4 To SB 14.318MHz NB CLOCKS RX780 RS780
CLKREQ1# REF1/SEL_SATA EXT_SB_OSC 10
B T49 CLKREQ2# 44 57 SEL_27 R279 158/F_4 To NB 14.318MHz B
CLKREQ2# REF2/SEL_27 EXT_NB_OSC 8
R222 8.2K_4 CLK_PD# T54 CLKREQ3# 39 HT_REFCLKP 100M DIFF 100M DIFF
CLKREQ4# CLKREQ3# R278 90.9/F_4
T48 38 CLKREQ4#
+3V HT_REFCLKN 100M DIFF 100M DIFF
TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9
REFCLK_P 14M SE (1.8V) 14M SE (1.1V)
SLG8SP628 R4004/R4005 (value may change) REFCLK_N NC vref
65
66
67
68
69
70
71
72
73
74
R165 NB_OSC GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
10K_4 RES CHIP 82.5 1/16W +-1%(0402) --> CS08252FB11 GPP_REFCLK 100M DIFF NC or 100M DIFF OUTPUT
EC A30 RX780 1.8V 82.5R/130R RES CHIP 130 1/16W +-1%(0402)L-F --> CS11302FB15
CLKREQ4# GPPSB_REFCLK 100M DIFF 100M DIFF
19 PCIE_REQ_LAN#
RES CHIP 158 1/16W +-1%(0402) --> CS11582FB00
RS780 1.1V 158R/90.9R RES CHIP 90.9 1/16W +-1%(0402) --> CS09092FB15
+3V +3V_CLK_VDD
CLK_48M_USB_R C355 *10P_4
R214 1 66 MHz 3.3V single ended HTT clock
R164 *8.2K_4 SEL_HTT66 SEL_SATA C313 *10P_4
0* 100 MHz differential HTT clock
10K_4
SEL_SATA 1 100 MHz non-spreading differential SRC clock SEL_27 C359 *10P_4
CLKREQ3# SEL_SATA
24 PCIE_REQ_WWAN#
SEL_HTT66 0 * 100 MHz spreading differential SRC clock
SEL_27 1 27MHz and 27M SS outputs EMI Cap placement close IC
+3V SEL_27
A A
0* 100 MHz SRC clock
R237 R248 R280
8.2K_4 8.2K_4 8.2K_4 * default
R176
10K_4
Quanta Computer Inc.
CLKREQ2#
23 PCIE_REQ_WLAN#
PROJECT : Congo
Size Document Number Rev
1A
CLOCK GEN SLG8SP628
Date: Thursday, October 22, 2009 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1
+1.2V_VLDT
D U26A D
AL4 VLDT_B4 VLDT_A4 F4
AL3 VLDT_B3 VLDT_A3 F3
AL2 VLDT_B2 VLDT_A2 F2
AL1 F1 C31 4.7U/6.3V_6
VLDT_B1 VLDT_A1
7 HT_CADINP15 Y6 L0_CADIN_H15 L0_CADOUT_H15 Y9 HT_CADOUTP15 7
7 HT_CADINN15 Y5 L0_CADIN_L15 L0_CADOUT_L15 Y8 HT_CADOUTN15 7
7 HT_CADINP14 W7 L0_CADIN_H14 L0_CADOUT_H14 AB6 HT_CADOUTP14 7
7 HT_CADINN14 W6 L0_CADIN_L14 L0_CADOUT_L14 AB5 HT_CADOUTN14 7
7 HT_CADINP13 U6 L0_CADIN_H13 L0_CADOUT_H13 AC7 HT_CADOUTP13 7
7 HT_CADINN13 U5 L0_CADIN_L13 L0_CADOUT_L13 AC6 HT_CADOUTN13 7
R7 AE6
7
7
7
HT_CADINP12
HT_CADINN12
HT_CADINP11
R6
M8
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
AE5
AE9
HT_CADOUTP12 7
HT_CADOUTN12 7
HT_CADOUTP11 7
+1.2V +1.2V_VLDT Place close to socket
7 HT_CADINN11 M7 L0_CADIN_L11 L0_CADOUT_L11 AE8 HT_CADOUTN11 7
L6 AH3 HT_CADOUTP10 7 L4
7 HT_CADINP10 L0_CADIN_H10 L0_CADOUT_H10
7 HT_CADINN10 L5 L0_CADIN_L10 L0_CADOUT_L10 AH4 HT_CADOUTN10 7
J6 AK3 HT_CADOUTP9 7 BLM21PG300SN1D_8
7 HT_CADINP9 L0_CADIN_H9 L0_CADOUT_H9
7 HT_CADINN9 J5 L0_CADIN_L9 L0_CADOUT_L9 AK4 HT_CADOUTN9 7
H4 AK1 HT_CADOUTP8 7 C10 C13 C8 C15 C14 C16
7 HT_CADINP8 L0_CADIN_H8 L0_CADOUT_H8
7 HT_CADINN8 H3 L0_CADIN_L8 L0_CADOUT_L8 AK2 HT_CADOUTN8 7
HT LINK
T3 Y1 HT_CADOUTP7 7 4.7U/6.3V_6 4.7U/6.3V_6 0.22U/6.3V_4 0.22U/6.3V_4 180P/50V_4 180P/50V_4
C 7 HT_CADINP7 L0_CADIN_H7 L0_CADOUT_H7 C
7 HT_CADINN7 T4 L0_CADIN_L7 L0_CADOUT_L7 Y2 HT_CADOUTN7 7
7 HT_CADINP6 T2 L0_CADIN_H6 L0_CADOUT_H6 Y4 HT_CADOUTP6 7
7 HT_CADINN6 T1 L0_CADIN_L6 L0_CADOUT_L6 Y3 HT_CADOUTN6 7
7 HT_CADINP5 P3 L0_CADIN_H5 L0_CADOUT_H5 AB1 HT_CADOUTP5 7
7 HT_CADINN5 P4 L0_CADIN_L5 L0_CADOUT_L5 AB2 HT_CADOUTN5 7
7 HT_CADINP4 P2 L0_CADIN_H4 L0_CADOUT_H4 AB4 HT_CADOUTP4 7
7 HT_CADINN4 P1 L0_CADIN_L4 L0_CADOUT_L4 AB3 HT_CADOUTN4 7 DESIGN NOTE:
M2 AD4
7
7
HT_CADINP3
HT_CADINN3 M1
L0_CADIN_H3 L0_CADOUT_H3
AD3
HT_CADOUTP3 7
HT_CADOUTN3 7
VLDT must be routed as a pour or a trace at least 200 mils wide.
L0_CADIN_L3 L0_CADOUT_L3
7 HT_CADINP2 K3 L0_CADIN_H2 L0_CADOUT_H2 AF1 HT_CADOUTP2 7 VLDT may be routed from the source to either ALx balls or Fx balls.
K4 AF2
7
7
HT_CADINN2
HT_CADINP1 K2
L0_CADIN_L2 L0_CADOUT_L2
AF4
HT_CADOUTN2 7
HT_CADOUTP1 7
Choose whichever makes routing simpler.
L0_CADIN_H1 L0_CADOUT_H1
7 HT_CADINN1 K1 L0_CADIN_L1 L0_CADOUT_L1 AF3 HT_CADOUTN1 7 These six capacitors must be placed very near the selected balls.
H2 AH1
7 HT_CADINP0
H1
L0_CADIN_H0 L0_CADOUT_H0
AH2
HT_CADOUTP0 7
HT_CADOUTN0 7
The "other" set of balls must be decoupled with a 4.7uF cap.
7 HT_CADINN0 L0_CADIN_L0 L0_CADOUT_L0
7 HT_CLKINP1 P6 L0_CLKIN_H1 L0_CLKOUT_H1 AF6 HT_CLKOUTP1 7
7 HT_CLKINN1 P5 L0_CLKIN_L1 L0_CLKOUT_L1 AF5 HT_CLKOUTN1 7
7 HT_CLKINP0 M3 L0_CLKIN_H0 L0_CLKOUT_H0 AD1 HT_CLKOUTP0 7
7 HT_CLKINN0 M4 L0_CLKIN_L0 L0_CLKOUT_L0 AD2 HT_CLKOUTN0 7
7 HT_CTLINP1 P8 L0_CTLIN_H1 L0_CTLOUT_H1 AB8 HT_CTLOUTP1 7
B 7 HT_CTLINN1 P9 L0_CTLIN_L1 L0_CTLOUT_L1 AB9 HT_CTLOUTN1 7 B
7 HT_CTLINP0 V2 L0_CTLIN_H0 L0_CTLOUT_H0 V4 HT_CTLOUTP0 7
7 HT_CTLINN0 V1 L0_CTLIN_L0 L0_CTLOUT_L0 V3 HT_CTLOUTN0 7
AM2-BGA-27-27-812-01
C26 D26 E26 F26 G26 H26 J26 K26 L26 M26 N26 P26 R26 T26 U26 V26 W26 Y26 AA26 AB26 AC26 AD26
B25 C25 D25 E25 F25 G25 H25 J25 K25 L25 M25 N25 P25 R25 T25 U25 V25 W25 Y25 AA25 AB25 AC25 AD25 AE25
A24 B24 C24 D24 E24 F24 G24 H24 J24 K24 L24 M24 N24 P24 R24 T24 U24 V24 W24 Y24 AA24 AB24 AC24 AD24 AE24 AF24
A23 B23 C23 D23 E23 F23 G23 H23 J23 K23 L23 M23 N23 P23 R23 T23 U23 V23 W23 Y23 AA23 AB23 AC23 AD23 AE23 AF23
A22 B22 C22 D22 E22 F22 G22 H22 J22 K22 L22 M22 N22 P22 R22 T22 U22 V22 W22 Y22 AA22 AB22 AC22 AD22 AE22 AF22
A21 B21 C21 D21 E21 F21 G21 H21 J21 K21 L21 M21 N21 P21 R21 T21 U21 V21 W21 Y21 AA21 AB21 AC21 AD21 AE21 AF21
A20 B20 C20 D20 E20 F20 H20 J20 K20 L20 M20 N20 P20 R20 T20 U20 V20 Y20 AA20 AB20 AC20 AD20 AE20 AF20
A19 B19 C19 D19 E19 F19 H19 J19 K19 L19 M19 N19 P19 R19 T19 U19 V19 Y19 AA19 AB19 AC19 AD19 AE19 AF19
A18 B18 C18 D18 E18 F18 G18 H18 J18 K18 L18 M18 N18 P18 R18 T18 U18 V18 W18 Y18 AA18 AB18 AC18 AD18 AE18 AF18
A17 B17 C17 D17 E17 F17 G17 H17 J17 K17 L17 M17 N17 P17 R17 T17 U17 V17 W17 Y17 AA17 AB17 AC17 AD17 AE17 AF17
A16 B16 C16 D16 E16 F16 G16 H16 J16 K16 L16 M16 N16 P16 R16 T16 U16 V16 W16 Y16 AA16 AB16 AC16 AD16 AE16 AF16
A15 B15 C15 D15 E15 F15 G15 H15 J15 K15 L15 T15 U15 V15 W15 Y15 AA15 AB15 AC15 AD15 AE15 AF15
A14 B14 C14 D14 E14 F14 G14 H14 J14 K14 L14 T14 U14 V14 W14 Y14 AA14 AB14 AC14 AD14 AE14 AF14
A13 B13 C13 D13 E13 F13 G13 H13 J13 K13 L13 T13 U13 V13 W13 Y13 AA13 AB13 AC13 AD13 AE13 AF13
A A
A12 B12 C12 D12 E12 F12 G12 H12 J12 K12 L12 T12 U12 V12 W12 Y12 AA12 AB12 AC12 AD12 AE12 AF12
A11 B11 C11 D11 E11 F11 G11 H11 J11 K11 L11 M11 N11 P11 R11 T11 U11 V11 W11 Y11 AA11 AB11 AC11 AD11 AE11 AF11
A10 B10 C10 D10 E10 F10 G10 H10 J10 K10 L10 M10 N10 P10 R10 T10 U10 V10 W10 Y10 AA10 AB10 AC10 AD10 AE10 AF10
A9 B9 C9 D9 E9 F9 G9 H9 J9 K9 L9 M9 N9 P9 R9 T9 U9 V9 W9 Y9 AA9 AB9 AC9 AD9 AE9 AF9
A8 B8 C8 D8 E8 F8 H8 J8 K8 L8 M8 N8 P8 R8 T8 U8 V8 W8 AA8 AB8 AC8 AD8 AE8 AF8
A7 B7 C7 D7 E7 F7 H7 J7 K7 L7 M7 N7 P7 R7 T7 U7 V7 W7 AA7 AB7 AC7 AD7 AE7 AF7
A6 B6 C6 D6 E6 F6 G6 H6 J6 K6 L6 M6 N6 P6 R6 T6 U6 V6 W6 Y6 AA6 AB6 AC6 AD6 AE6 AF6
CPU Quanta Computer Inc.
A5 B5 C5 D5 E5 F5 G5 H5 J5 K5 L5 M5 N5 P5 R5 T5 U5 V5 W5 Y5 AA5 AB5 AC5 AD5 AE5 AF5
A4 B4 C4 D4 E4 F4 G4 H4 J4 K4 L4 M4 N4 P4 R4 T4 U4 V4 W4 Y4 AA4 AB4 AC4 AD4 AE4 AF4
A3 B3 C3 D3 E3 F3 G3 H3 J3 K3 L3 M3 N3 P3 R3 T3 U3 V3 W3 Y3 AA3 AB3 AC3 AD3 AE3
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