Service Manuals, User Guides, Schematic Diagrams or docs for : LG Audio FL-R888K FL-R88~4
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download FL-R88~4 documenatation <<
Text preview - extract from the document
INTERNAL BLOCK DIAGRAM OF ICs
l BA3830S (lCl26) l BA6209 (IC504,505)
Reff erence
Ro2 1 - Current RESET
LINE
NF
l CXDI 178Q (ICI)
(LBB)RO
Rl
R2
R3
R4
R5 r--@) RCK
R6
R7
REC wB)oO
LEVEL Gl
&Bias
I I
62
63
VCC 64
G5
66
G7
(LSB)BO
Bl
82
83
1
84
85
86
87
BLK
l CXAl571S (IC501)
RF
SUMMING AMP
tl VEE I - IFOCUS
10k
-
l CXA1372AQ (IC502)
3 DATA -
CB(
9XLT
cP(
3CLK
RFI (
RFO(
4IL DATA REGISTER lINPUT SHIFT REGISTER
*ADDRESS DECODER
DVEE (
J
-
*OUTPUT DECODER
TZC (
lFSlQ lTGl-2 lTMl-7 lPSl-3
t 1 II
TEl . *TRACKING
. PHASE COMPENSATION I*&STOP
TDFCT ( TM1 - I I
TT 4
ATSC ( k lBPF - *WINDOW COMPARATOR -
`FOCUS
PHASE
COMPENSATION
FZC ( )
FE(
FDFCT (
3
8
29
l CXAI 645M (IC2)
`I OUT m MIX 11 I DRIVERHI DRIVERI ,-,I I
9 9
R-OUT G-OUT
I I t 1 DELAY H CLAMPH ;;; r
1 REGULATOR tJ
- R-Y
1 Modulator
t
I
B-Y L
I Modulator
FL SIN-PULSE
CXD2500BQ (IC506)
CXM
a
c16M
-- PO0
32KRAM 821 AVm
VCOI
VCOO
PC0 B
a
FKI
FILO
CLlv
RF
ASYI
ASYO MUTE
ASYE
WFCK
SCOA
EXCK
SBSC
EMOH
SOCK
SOS0
MON
FSW
MOP
DATO
MDS
CLKO
XLTO
TEST
NC
30
KA9258D (IC503)
LEVEL
SHIFT
PIN DISCRIPTION
PIN CONFIGURATION
I Pin No. I Symbol I 110 I Description
I 1 I DO1 .l I 0 I DRIVE OUTPUT
I 2 I Dol.2 I 0 I DRIVE OUTPUT
I 3 I Dll .l I I I DRIVE INPUT
r- 4 I D11.2 I I I DRIVE INPUT
I 5 I REG I I REGULATOR
I 6 1 REO I 0 I REGULATOR OUTPUT
I 7 I MUTE I I MUTE
I 8 I GNDl I I GROUND
I 9 I 012.1 I I I DRIVE INPUT
I 10 I D12.2 I I I DRIVE INPUT
I 11 I 002.1 I 0 I DRIVE OUTPUT
I 12 I 002.2 I 0 I DRIVE OUTPUT
I 13 I GNDZ I I GROUND
I 14 I OPOUT I 0 I OPAMP OUTPUT
15 I OPIN(-) I OPAMP OUTPUT(-)
16 OPIN(+) I OPAMP INPUT(+)
17 003.1 0 DRIVE OUTPUT
18 003.2 0 DRIVE OUTPUT
19 013.1 I DRIVE INPUT
20 D13.2 I DRIVE INPUT
21 VCCl SUPPLY VOLTAGE
22 vcc2 SUPPLY VOLTAGE
23 VREF 2.5V BIAS VOLTAGE
24 D14.1 I DRIVE INPUT
25 014.2 I DRIVE INPUT
26 004.1 0 DRIVE OUTPUT
27 D04.2 0 DRIVE OUTPUT
28 GND3 GROUND
l MMl093PF (IC6)
Base gate APC2
Filter Filter
-
I
4fso
vcc
I i--+In I f. 1
ACC APCl X'tal GNDl GND2 NC
Filter Filter
- l MN6790 (IC9) l M6583lP (IC805)
1 EXTERNAL 1
0 PIN CONFIGURATION
"DD "cc
XIN LPFl IN
XOUT LPFlOUT
PHASE TEST2
COMPARATOR -
Dl/REQ OPl OUT
D2/SCK OPl IN
PC2 5
D3lDATA REF
D4ll DSW cc1
TEST CC2
EASY/MICROCOMPUTER OP2lN
SLEEP OP20UT
D-GND LPF2lN
A-GND
J
-
@) IC INTERNAL BLOCK DIAGRAM
LPFlINLPFlOUT OPlOUT OPlIN CC2 OP21N OP20UTLPF2lN LPF20UT
REF
1 l/2 vcc 1 Dl DO0 DO1
i
I I _ MAIN CONTROL MO . + 46K-bit
AUTO CLOCK DELC MI - . SRAM
i
8 RESET L b
XIN XOUT Dl/REQ 1 D3/DATA 1 TEST1 SLEEP D-GND 1 VDDvcc
DIZ/SCK 04/l DSW EASY/ A-GND
MICROCOMPUTER
32
l NJM2248 (W 8) l NJM2257 (IC7)
VCC
C Sync OUT
GND VOUT V' i/IN3 VCC
-
VIDEO IN
I
-,__2.
Separation Timing
I .
I I +
Field
L Detect
* I I l Phase l l 32fH I IAFC. HD I A
AFC HD OUT
VINl SW1 VIN2 SW2
% I GND
HD OUT
-
l NJM2267 (IC12)
-
VOUT2
(6dB)
VIN2 8
VOUT2
r1
A VOUT2
75OQ
2.2k Q -VSAG2
2.0k Q SAG Compensation Port
VOUTI
(6dB)
VINl
VOUTI
IOOuF 1
I I v w
\
\- I
b
IIMI & 2.2kQ VSAGl
* 2.0k Q SAG Compensation Port 22uF
-
GND
33
o TDA1306T (lC223)
CLKSl CLK!32
I I
I
+ t
12
0 TIMING + - SYSCLK
w Ir
6 c
DATA -
-b SERIAL
5 , 4fs DIGITAL UP-SAMPLE'
ws - DATA
-+ INPUT FILTER AND FEATURES -AWL
4 %I
BCK - -APPO
-APPl
1 k
-APP2
. -APP3
TDA 1306T
TEST1
- "ODD
FILTt
20 FLTCR
I
1nF %ONV2 1
3k&! l
1 nF
, cc
DIVIDER
1 _L
"( a "OR
"I
J ' I I
%so "000 VWA %A
l pPD6376 (lC224,
-
LOUT
L.REF
N.C D.V DD A.GND A.V w
34
l GD74HCOOD (IC117)
-
INPUTS OUTPUT
1
Dna
L Dnb q
L L H
L H H
H L H
H H L
H=High voltage level
L=Low voltage level
TOP VIEW VCC `Pin14
GNDVin7
l GD74HC04D (ICIIO, 140)
PIN CONFIGURATION
-
1 2
IA 1 IA IV I INPUT 1 OUTPUT 1
IY 2
2A
3 4
2Y
I A I v I
2A 3
2Y 4
3A 5
3A
5
6 3Y k I : I
9 8 H-High voltage level
3v 4A 4Y L=Low voltage level
11
i 5A `O 5v
TOP VIEW -
12
6A l3 6y
VCC* Pin14
GND* Pin7
oGD74HC32D (IC15,109,118,119,219)
PIN CONFIGURATION LOGIC DIAGRAM FUNCTION TABLE
-
DOa Vcc INPUTS OUTPUTS
DOb D3b Dna Dnb
Ql
QO D3a L L L
D la
Q3 L H H
Dlb D2b H L H
Ql D2a H H H
GND Q2 H=High voltage level
L=Low voltage level
TOP VIEW
Vcc 3: Pin14
GND = Pin7
35
l 74HC08D (IC151)
PIN CONFIGURATION
- I
TiJ v, I INPUTS 1 OUTPUT 1
fl D3b
I D, Dnb 1 Qn I
121 D3a
TJ Q3
161 D2b
Ql Is 1 D2a
GNDE 81 Q2 H=High vottage level
L=Low voltage level
TOP VIEW V~C+in14
GND- pin 7
l 74HCl23 (ICliy13)
Pin Configuration Functional symbol Function Table
INPUTS OUTPUTS
7
16 "cc
lCEXT 14
lREXTK EXT 15 nCLR nA nB nQ no
7
15 lR EXTK:EXT
PR L X X L H
Ql 1Q 13
7
14 1c
EXT
X H X L H
TzrL Ob 1u 4
4 7
13 1Q
CLR X X L L H
- 123
5 7
12 z 3 1CLR I
- H L t
XEXT 6
2R EXT "
*' EXT
EXT
-
6
7
11
7
10
7
PCLR
28
Y
2REXTICEXT 7 H
t
4
L
H
H
8 79 2x JL = one HIGH level output pulse
V = one LOW level output pulse
l 74HCl38D (IC213)
LOGIC DIAGRAM DECODER FUNCTION TABLE
INPUTS OUTPUTS
4
A0 4 A2 a() cl, a, 8, cl4 8, cl, cl7
Al
H X X x xx HHHHHHHH
A0
x H x x xx HHHHHHHH
EO
5 x x L x xx HHHHHHHH
E2
L L H L L L LHHHHHHH
L L H H L L HLHHHHHH
L L H L HL HHLHHHHH
"cc = Pin 16
L L H HHL HHHLHHHH
GND = Pin 16
L L H L LH HHHHLHHH
L L H H L H HHHHHLHH
L L H L HH HHHHHHLH
i L L H -- H HH HHHHHHHL
H = High voltage level
L = Low voltage level
X = Don'tcare
36
l 74HCl57 (IC217)
FUNCTION TABLE
-
s F-J-3 kc
`O ,?, `O b `l b `0 ~ `1 ~ `O d `l d r 3
INPUTS OUTPUT
El SI IOn Iln yn
IOa 2
d
`la d3
LIHlXlLl L
LlHlXlHl H
LILILIXI L
LILIHIXI H
H= High voltage level
L = Low voltage level
X =Don't care
`b `d
SC = Pin 16
GND = Pin 8
l 74HC164D (El 6)
LOGIC DIAGRAM
D sa '
t
2 L. -D Q- -D Q- -D Q- -D Q- -D Q- -D Q-
Dsb
RD RD RD RD RD RD RD
i 13
C C Q7
VCC=Pin14
GND= Pin 7
FUNCTION TABLE
INPUTS OUTPUTS
OPERATING MODE
6k CP &a Dsb Qg Q1----Q7
L x x x LL L Reset (clear)
H t I I L 90 96
H t I h L 90
qs l Shift
H t h I L 90 q6
H t h h H 90 q6
`H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
I = Low voltage level one set-up time prior to the Low-to-High clock transition
qn = Lower case letters indicate the state of the referenced input (or output) on setup time prior
to the Low-to-High clock transition
x = Don't care
t = Low-to-High clock transition
37
l 74HC574D (ICI11 g214)
LOGIC DIAGRAM
-
Do Dl D2 D3 D4 D5 D6 D7
2 3 4 5 6 7 8 9
.
P
# 4 , f
D -D -D -D -D -D -D LD
CP G _CP a_ ,CP G, _CP c,, _CP G, ,CP a, _CP iz;, -CP d,
, , I .
* -&
6i +
I14 I13 I12
w w v - w w
I19 I18 I 17 I 16 I 15
QO Ql Q2 Q3 Q4 Q5 Q6 Q7
~CC = Pin20
GND-Pin10
FUNCTION TABLE
INPUTS 1 INTERNAL OUTPUTS
OPERATING MODE
Qo l
Q7
L
Load and read registor
H
L NC
Hold
H 1 1 Dn 1 Dn Z
Disable outputs
H x I x I X Z
H = High voltage level
h = High voltage level one set up time prior to the Low to High clock transition
L = Low voltage level
I = Low voltage level one set up time prior to the Low to High clock transition
NC = No change
X = Don'tcare
Z = High impedance "off" state
t = Low to High clock transition
t = Not a Low to High clock transition
l 74HC86D (IC220)
PIN CONFIGURATION LOGIC DIAGRAM FUNCTION TABLE
INPUTS 1 OUTPUT
D
na
Dnb I %
H=High voltage level
VCC = Pin14 L=Low voltage level
GND = Pin7
TOP VIEW
38
◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo