Service Manuals, User Guides, Schematic Diagrams or docs for : LG Car Audio tcc-8010 internal block diagram of lcs
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5. INTERNAL BLOCK DIAGRAM of Ics
s IC101 DBL 1018
IF Quad V
VCC Out In ref
12 9 11 13
VOLTAGE
AFC
REGULATOR 7 AFC
CLAMF
IF Input 1 1st 2nd 3rd 4th 5th 6th OUAD OUADRATURE
Amp Amp Amp Amp Amp Amp LIMITER DETECTOR
2
Bias
3
AF AF
8 Output
MUTE
LEVEL LEVEL LEVEL HOLE DC LEVEL Amp 5 Mute
Attenuation
DETECTOR DETECTOR DETECTOR INVERTER DETECTOR DETECTOR Adjust
GND 4
SIGNAL
AGC MUTE
METER
DRIVE DRIVE
DRIVE
16 15 14 10 6
AGC Signal Mute GND Mute
Meter Drive Input
Output
s IC201 DBL 1019
Local OSC Local Local IF Signal Signal Detector Detector
Butter Out OSC2 OSC1 AGC Meter Out Meter In VCC Out GND In
20 19 18 17 16 15 14 13 12 11
IF
LOCAL DETECTOR
LOCAL IF SIGNAL
OSC
OSC AGC METER
BUFFER
ALC
RF DETECTOR
IF
RF ATTENUATOR MIX
RF RF AMP
AGC AMP2 DRIVER AMP2
1 2 3 4 5 6 7 8 9 10
RFAGC RFAmp2 RF ANT Damping GND MIX in & MIX VCC IF Amp IF Amp
Out In AGC Driver RF AMP1 In Out In Out
- 11 -
s IC301 KIA6043S
2 4
1 AF PHASE DC
INPUT DETECTOR VCO 76kHz 1/2 1/2
19kHz<90
PILOT TRIGGER STEREO
DETECTOR SWITCH 1/2
19kHz<0
STEREO STABILZED
DECODER 38kHz POWER SUPPLY
4V 4V 7.4V
8 9 7 6 5 3
LEFT RIGHT L.P.F-2 GND
s IC401 KIC9256P
VDD GND
FM L 9 12
PSC
AMP
FM IN 11 1/2 2 MODULUS 4 bit SWALLOW POWER ON
PRESCALER COUNTER RESET
FMS HF RESET
AM IN 10 12 bit PROGRAMMABLE COUNTER COMPARATOR TRI-STATE 15 DO1
FM MODE LF BUFFER
PHASE
12
4
XT 2 OSC
REFERENCE COUNTER TRI-STATE
CIRCUIT MAX BUFFER 16 DO2
XT 15 (DO2/OT-4)
1
1mS OSC 4 OT4
24bit REGISTER UNLOCK
DATA 5
1/0 PORT
5 1/0-5/CLK
24bit SHIFT REGISTER
CLOCK 4 8 1/0-6
TEST 5
ADDRESS
24 22
DECODER
PERIOD 3 10
24bit REGISTER 13 1/0-9 IFIN2
(1/0-6 IF IN2 )
4 4 AMP
20bit BINARY COUNTER 1/0-8 IF
IN1
14 (1/0-5 IF
OUTPUT PORT UNIVERSAL COUNTER CONTROL
AMP IN1 )
GATE
1/0-7 SC IN
OT-4
XT 1mS
6 7 8
OT-1 OT-2 OT-3 OT-4
NOTE: Mark terminals are not existence in KIC9256P, KIC9256F
Terminal name of KIC9256P, KIC9256F is shown in parentheses.
Others are common terminals.
- 12 -
s IC402 uPD789166
1) Overall block diagram
FM IF MPX w/SNC E-VOL. POWER
FM TUNER
LA1140 Hcc TDA7313 IC
PLL IC
KIC9256P
AM TUNER
u-COM
CIRCUIT LOGIC DECK
TCC-8010
TN
LCD DRIVER LCD DISPLAY
2) Pinning overview
UNLOAD
POWER
MOTOR
RESET
GND0
VDD0
F/R
NC
NC
X1
X2
33 32 31 30 29 28 27 26 25 24 23
LOAD 34 22 NC
RSENS1 35 21 MUT/LED
RSENS2 36 20 CDCDO
GND1 37 19 FCLK
CD ON 38 18 PDATA
EVCLK 39 uPD789166 17 VDD1
EVDATA 40 16 PCLK
MSSENS 41 15 FINH
NC 42 14 ACCIN
AVDD 43 13 CDCDI
AVREF 44 12 FCE
1 2 3 4 5 6 7 8 9 10 11
LEVELIN
TMOD3
TMOD2
TMOD1
FDATA
KEYIN
AGND
SDIN
PERI
STIN
NC
- 13 -
3) Pin function
PIN Port P-NAME I/O Act DESCRIPTION When not used REMARK
1 P60 NC NO CONNECTION
2 P61 TMOD3 I Tape mode detect input3
3 P62 TMOD2 I Tape mode detect input2
4 P63 TMOD1 I Tape mode detect input1
5 P64 SDIN I Tuner SEEK Stop detect input.
6 P65 STIN I FM Stereo detect input(LOW= ST ON)
7 P66 KEYIN I A/D Key input.
Used for also front panel detecting.
Less than 0.17V: regarded as the panel opened.
8 P67 LEVELIN I Dancing level detect input.
9 AGND Analog GROUND
10 P10 FDATA O Front(LCD driver) data communication output.
Diode matrix DIO IN0 line
11 P11 PERI O PLL IC Period communication output.
Diode matrix DIO OUT2 line
12 P30 FCE O Front(LCD driver) CE communication output.
I Diode matrix DIO IN1 line
13 P31 CDCDI I CD CHANGER Data input.
14 P32 ACCIN I L ACC Detect input(LOW = ACC ON)
15 P33 FINH O Front(LCD driver) INH communication output.
16 P20 PCLK O O PLL IC clock communication output.
Diode matrix DIO OUT0 line
17 VDD1
18 P21 PDATA O PLL IC data communication output.
Diode matrix DIO OUT1 line
19 P22 FCLK O Front(LCD driver) Clock communication output.
Diode matrix DIO IN2 line
20 P23 CDCDO O CD CHANGER Data output.
21 P24 MUT/LED O Used as power IC mute. (LOW = MUTE)
Used as blinking LED.
22 IC0
23 XT2
24 XT1
25 RESET
26 X2
27 X1
28 VSS0
29 VDD0
30 P25 POWER O H When system is on, this port is used as power out port.
31 P26 MOTOR O H Main motor out port.(HIGH = MOTOR ON )
32 P00 F/R O Direction select output.
LOW = Forward play.
High = Rewind play.
33 P01 UNLOAD O H Sub motor unload output.
34 P02 LOAD O H Sub motor load output.
35 P03 RSENS1 I Reel pulse1 input.
36 P04 RSENS2 I Reel pulse2 input.
37 VSS1
38 P05 CDON O H When CDC mode, this port is high output.
39 P50 EVCLK O Electric volume IC clock communiction output.
40 P51 EVDATA O Electric volume IC data communiction output.
41 P52 MSSENS O L When TAPE mode, this port is tape signal detect input.
42 P53 NC NO CONNECTION
43 AVDD Analog VDD
44 AVREF A/D convert reference voltage input.
- 14 -
s IC501 KIA2025
4 1
s IC502 FAN8082
GND 1 DRIVER OUT 8 VO2
VO1 2 7 PV CC
PRE DRIVER
V CTL 3 6 SV CC
TSD BIAS
V IN1 4 LOGIC SWITCH 5 V IN2
- 15 -
s IC601 PT2313L
LOUT LIN LOUD_L BOUT_L BIN_L TREB_L
17 16 12 19 18 4
Speaker
ATT
25 LFOUT
LIN1
LIN1 15 RB
Mute
LIN2
LIN2 14 Speaker
LIN3 Voume & ATT
LIN3 13 Bass Treble
Input Loudness
23 LROUT
Selector
Mute
RIN3
& Gain
RIN3 9
RIN2 Serial Bus Decoder & Latches 28 CLK
Control
RIN2 10
RIN1 27 DATA
RIN1 11 26 DGND
Speaker
ATT
Voume
Bass Treble
&
24 RFOUT
Loudness
Mute
RB Speaker
ATT
22 RROUT
Supply
Mute
2 3 1 7 6 8 21 20 5
VDD AGND REF ROUT RIN LOUD BOUT_R BIN_R TREB_R
- 16 -
s IC801 TDA8571J
MODE VP1 VP2 VP3 VP4
15 1 8 16 23
10
IN1 +
2
OUT1+
-
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