Service Manuals, User Guides, Schematic Diagrams or docs for : LG LCD LG ML038B CHASSIS LCD TV TRAINING MANUAL lg_ml038b_chassis_lcd_tv_training_manual_121
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LCD TV Technical Training Manual
ML-038B Chassis 30 inch LCD TV
- RT-30LZ13
(Market:China & the Middle East)
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Contents
1. Circuit operation Description
1.1 Block diagram
1.2 Signal Input block
1.3 Video Decoder Block
1.4 De-interlacer Block
1.5 A/D converter Block
1.6 Scalar input Block
1.7 Scalar output Block
1.8 Micro controller Block
1.9 Audio Circuits
2. Power Board block
2.1 Block diagram
2.2 Circuit Description
Appendix 1
1. Software Upgrade Method
2. Composite Signal Description
2.1 NTSC Composite Signal
2.2 PAL Composite Signal
2.3 SECAM Composite Signal
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1. Circuit operation Description
1.1 Block diagram:The fallowing diagram illustrates basic schematic of the chassis:
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1. Circuit operation Description
1.2 Signal input Block
*1.)
*5.)
*2.)
*4)
*3.)
This is a analog signal input circuit diagram:
This block consist of three SCART and one S-Video inputs.
*1) This is Full SCART Jack. Output signals from this jack are CVBS and R,G,B,FB.
Inputs are CVBS signal from tuner and audio inputs for R and L channels.
*2) This is Half SCART Jack. Input signal from this jack is CVBS only. And output signal is
video signal that currently is displayed on our LCD TV.
*3) This is Half SCART Jack. Input signal from this jack is CVBS only. And there is no output signal.
*4) This is S-Video signal input. 82 ohm resistors on the Video Signal line are used for impedance matching.
*5) This is analog video Switching IC. Five video input signals(Three SCART , one S-Video, one CVBS from
Tuner) are switched by this IC.
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1. Circuit operation Description
1.2 Signal input Block
*1)
This is a analog Tuner and associated circuit diagram:
This Tuner takes the input as the RF signal from cable or antenna and converts it into IF signal using Superheterodyning
process.
1) This Tuner can tune for PAL and SECAM RF signal
2) Power supply voltage for this tuner is 5V, 33V.
3) The inputs to the tuner is TV RF signal from coaxial cable and output is TV video signal which processed by video decoder
to be displayed on screen.
4) The most important functions associated are AGC(Automatic Gain Control) and AFT(Auto Frequency Tuning).
5) The SIF i.e.Sound IF is also given out by tuner which is then fed to audio section.
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1. Circuit operation Description
*3.)
*1.)
*2.)
This is a DVI signal input circuit diagram.
The jack is DVI-I Digital and Analog [RGB]; 29 pins.(For Its details and Pin out see Appendices at the end)
This block consist of TMDS input, SCL and SDA signals.
*1) This is a circuit for protection against the ESD.
*2) This is a TMDS signal input which are consist of 4 channels. 3 channel is for data and 1 is for clock.
*3) This is EEPROM which DVI EDID data is stored in.
The EDID should be stored in this EEPROM to boot up with the DVI signal input.
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1. Circuit operation Description
*2.)
*4.)
*1.)
*3.)
*5.)
This is Analog R,G,B signal and RS-232C port input Block.
This block consist of 3.3V regulator, 2.5V regulator, panel Vcc voltage switching circuit.
*1) This is a circuit for protection against the ESD.
*2) This is EEPROM which RGB EDID data is stored in.
The EDID should be stored in this EEPROM to boot up with the DVI signal input.
*3) This is RS-232C jack which is used for software-upgrade and white balance adjustment.
It is connected with PC for software-upgrade usage
or white balance adjustment equipment in manufacturing process.
*4) This is Level shifting IC. It is used to communicate between PC and our chassis's CPU.
*5) This is D-SUB jack.(For Its details and Pin out see Appendices at the end)
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1. Circuit operation Description
1.3 Video decoder Block
*2)
*1)
The main Features of *1) VPC3230 are have functions are
- high performance adaptive 4H Comb-Filter Y/C separator with adjustable vertical
* Input signal Format
peaking.
- multi-standard color decoder PAL/NTSC/SECAM including all sub standards. *1) CVBS Signal
- four CVBS, one S-Video input and one CVBS output (Y Signal+C Signal+H,V Sync)
- two RGB/YPbPr Component input, one Fast Blank input *2) S-Video Signal
- peaking,contrast,brightness,color saturation,tint for RGB/YPbPr and CVBS,S-Video
(Separated Y,C Signal)
- IC Bus interface
- one 20.25Mhz Crystal, few external components. *3) Component Signal ,Only 480i
- YUV 4:2:2 output format. (Y, Pb, Pr)
- *2) is I/P detector circuit. Only 480i signal pass through Video decoder IC.
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1. Circuit operation Description
1.4 Deinterlacer Block
*2)
*1)
This block consists of
*1)FLI2200(Deinterlacer/Line doubler).
*1) Removes artifacts produced by improper Y/C separation.
Supports 525/60(NTSC),625/50(PAL/SECAM).
Accept up to 1100 pixels/line
YUV,RGB or YCbCr progressive output options.
Supports 8 or 10 bit inputs and outputs.
Our chassis use 10 bit YUV output format.
*2) 64M SDRAM,
is Field memory which have 4MB capacity.
This IC's feature is a little different according to makers.
160Mhz Memory clock is used.
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1. Circuit operation Description
1.5 AD converter Block
*1)
This block consists of AD Converter,.
*1) 140M MSPS Maximum conversion rate.
0.5 to 1V Analog input range.
Component(480p,720p,1080i) /R,G,B signal pass through this IC.
Output format is R,G,B 8:8:8 format .
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1. Circuit operation Description
1.6 Scalar input Block
*2)
*1)
*1) Video port input Block.
Input data format is YUV 4:2:2 plus H,V sync and data clock .
Deinterlacer IC's output pass through this.
*2) Graphic port input Block.
AD Converter's output and TMDS receiver IC `s output pass through this.
AD Converter IC:AD9888, TMDS receiver:Sil161B.
Input data format is RGB 8:8:8 digital data signal plus H,V sync and data clock.
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1. Circuit operation Description
1.7 Scalar output Block
*2)
*1)
*3)
*1) is data output.
Data output format is composed of RGB 8:8:8, H,V sync, data clock,data enable.
Output sync and clock corresponds to LCD Module's timing.
*2) is LVDS transmitter IC.
Five pair signal data is transmitted to LCD Module's T-con Board.
*3) is FET IC for 12V power supply.
12/29
1. Circuit operation Description
1.8 Micro controller Block(CPU) *5)
*4)
*2
*3)
*1)
This block consists of CPU, Flash memory, SRAM, Port Expansion, etc ,.
*1) is CPU IC.
Use 3.3V-standby Power and 25Mhz clock.
It keep in communication with Flash memory,SRAM by 16bit parallel /
Scaler IC by 8bit parallel.
It keep in communication with EEPROM by I2C.
*2) is Port Expansion.
It receive local key input. Output control signal is inv_on, sound_mute and lvds_enable,etc.
*3) is Flash memory that stored in System file and OSD file.
*4) is SRAM that is loaded all kinds of variables.
*5) is EEPROM that stored in adjustment data and user control data.
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1. Circuit operation Description
1.9 Audio Block
*2)
*3)
*1)
This block consists of Multi Standard Audio Processor and Audio amplifier ,.
*1) This is the MSP audio processing IC,This IC performs processing of different standards.
It performs ASS (Automatic Standard Selection).
*2)They are Audio Amplifiers IC for Right and Left Audio Channels. It is a 20W class-D amplifier IC which operates
on 18Volts Vcc The efficiency is very high.
*3)The PC input jack is used to give Audio Inputs
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2. Power Board Block
2.1 Block Diagram
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