Service Manuals, User Guides, Schematic Diagrams or docs for : LG Laptop LG XNOTE E510 (Quanta PL3) laptop schematic
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1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP
01
LAYER 2 : SGND1
LAYER 3 : IN1 PL3 Block Diagram
LAYER 4 : IN2
A A
LAYER 5 : VCC
LAYER 6 : BOT Intel
CLOCK GENERATOR
Merom ICS9LPR363
(35W)
Page 3
Page 4,5
VCC_CORE
MAX8736 FSB(667/800MHZ)
R.G.B
CRT
VCC1.5 Page 14
G966
LVDS X1
LCD(WXGA 15.4) 533/ 667 MHZ DDR II
Page 14 DDRII-SODIMM1
VCC1.05
MAX1933 Crestline GM Page 15,16
B VCC1.25 DDRII-SODIMM2 B
Page 15,16
1.8VSUS
Page 6,7,8,9,10,11,12,13
TPS51116
3VPCU DMI(x2/x4)
RVCC3
3VSUS MINI PCIE
VCC3 SATA PCI-E, 1X
SATA - HDD USB4
5VPCU Page 25 Page 23
RVCC5
5VSUS PATA
IDE - ODD LAN(10/100M)
VCC5 Page 25 PCI-E, 1X M88E8039
MAXIM RJ45
Page 24 Page 24
MAX8744ETJ+ Page:26
USB 2.0
ICH8M
USB PORT 0
Page 29
C C
USB PORT 2
Page 29
Azalia
Page 17,18,19,20
USB PORT 6
Page 29
LPC INT SPK
32.768KHz AUDIO CODEC Page 27
MDC MAX 9789A
USB PORT 5
Page 29 4 IN 1 CARD CX20548-S CX20549-12Z Page 27 HP
(Optional) Page 27
PC8769 Ext MIC
Page 28 Page 26
Page 26
Page 31,32
RJ11
Page 28
D
FAN Touch Key FLASH D
PAD Board ROM
Quanta Computer Inc.
PCB P/N:DA0PL3MB6A7 PROJECT : PL3
Size Document Number Rev
A
Block Diagram
Date: Thursday, January 11, 2007 Sheet 1 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Page 01:
Page 02:
Page 03:
Block diagram
Table of contents
Clock generator ICS9PR363 Power Voltage
Voltage Rails
ON S0~S2 ON S3 ON S4 ON S5 Ctl Signal PCB STACK UP
2
Page 04: Merom(Host Bus) 9VPCU 9V V V V V
5VPCU 5V V V V V
LAYER 1 : TOP
Page 05: Merom(Power)
3VPCU 3V V V V V
LAYER 2 : GND
Page 06: CPU Thermal/Fan Control
A
LAYER 3 : IN1 A
Page 07: Crestline A(Host) RVCC3 3V V V V RVCC_ON LAYER 4 : IN2
Page 08: Crestline B(VGA,DMI)
LAYER 5 : VCC
Page 09: Crestline C(DDR2)
5VSUS 5V V V SUSON
LAYER 8 : BOT
Page 10: Crestline D(VCC)
Page 11: Crestline E(Power) 3VSUS 3V V V SUSON
Page 12: Crestline F(VSS) 1.8VSUS 1.8V V V SUSON
Page 13: Crestline (Straps) VCC5 5V V MAINON
PCI DEVICES IRQ ROUTING
Page 14: Panel LCD/CRT VCC3 3V V MAINON PCI ROUTING
Page 15: DDR2 SODIMM TABLE IDSEL INTERUPT DEVICE
Page 16: DDR2 Termination REQ0# / GNT0# AD17 INTA#,INTB# RICOH832
Page 17: ICH8M (Host)
Page 18: ICH8M (PCIE) VCC1.5 1.5V V MAINON
Page 19: ICH8M (GPIO) VCC1.25 1.25V V MAINON
Page 20: ICH8M (Power) VCC1.05 1.05V V MAINON
B B
Page 21: R5C832 (PCI) SMDDR_VTERM 0.9V V MAINON
Page 22: R5C832 (4in1)
Page 23: SD/MS/xD Connector VCC_CORE By CPU V VR_ON
Page 24: PCIE LAN 88E8039
Page 25: Mini PCIE/EMI
Page 26: SATA/ODD Connector
Page 27: CODEC(CX20549)
Page 28: Audio Amplifier MAX9789A Power On Sequence
Page 29: CONEXTANT MDC ACIN
Page 30: Kerboard/USB 5VPCU/3VPCU
Page 31: TP/LED/SW NBSWON#
Page 32: KBC uR PC8769
PWRBTN#
Page 33: KBC PC87541
Page 34: CPU CORE MAX8736
From 87541
C Page 35: VCC1.05 RVCC_ON C
Page 36: 1.8VSUS/VCC1.5/VCC1.25 From 87541
RSMRST#
Page 37: 3VPCU/5VPCU
Page 38: Battery Charger SUSB#,SUSC#
Page 39: Battery Connector From 87541
SUSON
From 87541
MAINON
VSUS,VCC
From 87541
VR_ON
VCORE_CPU
PWROK
D D
PCIRST#
Quanta Computer Inc.
PROJECT : PL3
Size Document Number Rev
A
System Information
Date: Wednesday, January 10, 2007 Sheet 2 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Clock Generator
A A
U5
VCC3 L10 BKP1608HS181-T VDD_CK_VCC3 ICS9LPRS365AGLFT/ SLG8SP512T
EMI FILTER BKP1608HS181-T(180,1.5A) IC(64P) ICS9LPRS365BGLFT(TSSOP)
C241 C188 C236 C384 C232 C235 C380 C192 2 48
VDD_PCI IO_VOUT
9 VDD_48
.1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 16 64 CGCLK_SMB
VDD_PLL3 SCLK CGCLK_SMB 15
10U_8 10U_8 61 63 CGDAT_SMB
VDD_REF SDA CGDAT_SMB 15
VDD_CK_VCC1.05 CK505
39 VDD_SRC SRC5/PCI_STOP# 38 PM_STPPCI# 19
55 VDD_CPU SRC5#/CPU_STOP# 37 PM_STPCPU# 19
VCC1.05 L12 BKP1608HS181-T VDD_CK_VCC1.05
12 54 CLK_CPU_BCLK_R RP35 1 2 0X2
VDD_96_IO CPU0 HCLK_CPU 4
EMI FILTER BKP1608HS181-T(180,1.5A) 20 53 CLK_CPU_BCLK#_R 3 4
VDD_PLL3_IO CPU0# HCLK_CPU# 4
C234 C190 C233 C189 C402 C381 C183 C240 26 VDD_SRC_IO_1 CLK_MCH_BCLK_R RP34
42 VSS_SRC3 CPU1 51 1 2 0X2 HCLK_MCH 7
36 50 CLK_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# HCLK_MCH# 7
0.1U close to each VDD_IO Power pin .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 .1U_4 10U_8 10U_8 49 VDD_CPU_IO
SRC8/ITP 47
SRC8#/ITP# 46
19 SATACLKREQ# R121 SATACLKREQ#_R
475_4 1 35 CLK_PCIE_3GPLL#_R 1 2
PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 8
34 CLK_PCIE_3GPLL_R RP36 3 4
SRC10 0X2 CLK_PCIE_3GPLL 8
T251 R113 *33_4PCLK_R5C832_R 3 PCI1/CR#_B PCIE_CLK_RBS_R R155 475_4
SRC11/CR#_H 33 CLK_MCH_OE# 8
R101 33_4 PCLK_MINI_R 4 32
23,31 PCLK_DEBUG PCI2/TME SRC11#/CR#_G
R298 33_4 PCLK_591_R 5 30 R_CLK_PCIE_LAN 3 4
31 PCLK_591 PCI3 SRC9 CLK_PCIE_LAN 24
31 R_CLK_PCIE_LAN# RP29 1 2
B SRC9# 0X2 CLK_PCIE_LAN# 24 B
PCI_CLK_SIO_R 6 PCI4/SRC5_EN
SRC7/CR#_F 44
PCLK_ICH_R 7 43
PCIF5/ITP_EN SRC7#/CR#_E
C222 33P_4 CG_XIN 60 41 CLK_PCIE_ICH_R RP37 1 2 0X2
XTAL_IN SRC6 CLK_PCIE_ICH 18
40 CLK_PCIE_ICH#_R 3 4
SRC6# CLK_PCIE_ICH# 18
2
Y1 CG_XOUT 59 XTAL_OUT CLK_PCIE_MINI_R RP30
XTAL length < 500mils SRC4 27 3 4 0X2 CLK_PCIE_MINI 23
14.318MHZ R123 33_4 FSA 10 28 CLK_PCIE_MINI#_R 1 2
USB_48/FSA SRC4# CLK_PCIE_MINI# 23
1
C217 33P_4 CPU_BSEL1 57 24
FSB/TEST/MODE SRC3/CR#_C
SRC3#/CR#_D 25
FSC 62
19 CLKUSB_48 REF0/FSC/TESTSEL CLK_PCIE_SATA_R RP28
SRC2/SATA 21 3 4 0X2 CLK_PCIE_SATA 17
CPU_BSEL0 R110 2.2K_4 8 22 CLK_PCIE_SATA#_R 1 2
VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 17
CPU_BSEL2 R158 10K_4 11 VSS_48 DREFSSCLK_R
15 VSS_IO SRC1/SE1 17 3 4 DREFSSCLK 8
R159 22_4 19 18 DREFSSCLK#_R 1 2
19 14M_ICH VSS_PLL3 SRC1#/SE2 RP31 0X2 DREFSSCLK# 8
52 VSS_CPU
23 13 DREFCLK_R 3 4
VSS_SRC1 SRC0/DOT96 DREFCLK 8
29 14 DREFCLK#_R 1 2
VSS_SRC2 SRC0#/DOT96# RP32 0X2 DREFCLK# 8
VDD_CK_VCC1.05 45 VDD_SRC_IO_3
58 VSS_REF CKPWRGD/PWRDWN# 56
CK_PWG 19
ICS9LPRS365BGLFT:ALPRS365K13
During initial power-up be used to
SLG8SP512T: AL8SP512K05
sample FSB speed with FSA/B/C
C C
Clock Gen I2C
VCC3
R109 0_4 CPU_BSEL0_ R108 0_4
4 CPU_BSEL0 MCH_BSEL0 8 BSEL Frequency Select Table
VCC1.05 R107 *56_4
FSC FSB FSA Frequency
R95 1K_4 R153 R154
R310 0_4 CPU_BSEL1_ R165 0_4 0 0 0 266Mhz 10K_4 10K_4 Q6
4 CPU_BSEL1 MCH_BSEL1 8
2
2N7002E
R161 *0_4
0 0 1 133Mhz CGCLK_SMB 1 3 PCLK_SMB 19,23
VCC1.05 R157 1K_4
4 CPU_BSEL2
R173 0_4 CPU_BSEL2_ R162 0_4 0 1 1 166Mhz
MCH_BSEL2 8
VCC3
R164 *0_4 change1:clock to data wrong connection b-test
0 1 0 200Mhz Q5
2
VCC1.05 R163 1K_4 2N7002E
1 1 0 400Mhz CGDAT_SMB 1 3 PDAT_SMB 19,23
1 1 1 Reserved
VCC3
1 0 1 100Mhz
D D
1 0 0 333Mhz PCLK_MINI_R R297 10K_4
PCLK_ICH_R R94 *10K_4
PCI_CLK_SIO_R R124 *10K_4
SATACLKREQ#_R R122 10K_4
PCIE_CLK_RBS_R R156 10K_4
PCLK_ICH_R R93 10K_4
Quanta Computer Inc.
PCI_CLK_SIO_R R112 10K_4
PROJECT : PL3
Size Document Number Rev
A
Clock Generator
Date: Wednesday, January 10, 2007 Sheet 3 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
7 H_A#[3..16]
H_A#[3..16]
H_A#3
H_A#4
J4
L5
U16A
A[3]#
A[4]#
ADS#
BNR#
H1
E2
H_ADS#
H_BNR#
7
7
7 H_D#[0..63]
H_D#[0..63]
H_D#0
H_D#1
E22
F24
U16B
D[0]#
D[1]#
D[32]#
D[33]#
Y22
AB24
H_D#32
H_D#33
H_D#[0..63] 4
H_A#5 L4 G5 H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# 7 D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# 7 F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_D#5 G25 T22 H_D#37
A[8]# DRDY# H_DRDY# 7 D[5]# D[37]#
H_A#9 J1 E1 H_D#6 E25 U25 H_D#38
A[9]# DBSY# H_DBSY# 7 D[6]# D[38]#
H_A#10 N3 H_D#7 E23 U23 H_D#39
A A[10]# D[7]# D[39]# A
ADDR GROUP 0
ADDR GROUP 0
DATA GRP 0
DATA GRP 2
H_A#11 P5 F1 H_D#8 K24 Y25 H_D#40
A[11]# BR0# H_BR0# 7 D[8]# D[40]#
H_A#12 P2 H_D#9 G24 W22 H_D#41
H_A#13 A[12]# H_IERR# R105 1 D[9]# D[41]#
L2 D20 2 56_4 H_D#10 J24 Y23 H_D#42
CONTROL
A[13]# IERR# VCC1.05 D[10]# D[42]#
H_A#14 P4 B3 H_D#11 J23 W24 H_D#43
A[14]# INIT# H_INIT# 17 D[11]# D[43]#
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# 7 F26 D[13]# D[45]# AA23
M1 H_D#14 K22 AA24 H_D#46
7 H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# D[14]# D[46]#
C1 H_RESET# H_D#15 H23 AB25 H_D#47
7 H_REQ#[0..4] RESET# H_RESET# 7 D[15]# D[47]#
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