Service Manuals, User Guides, Schematic Diagrams or docs for : PACKARD BELL Packard Bell easynote sl81 sl51 ml61 Quanta PF1-2-PF1Q
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5 4 3 2 1
PF1/2/PF1Q BLOCK DIAGRAM PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND
01
HOST 200MHz
DDRII-SODIMM1 CPU_CLK LAYER 3 : IN1
AMD S1g2 CLOCK GENERATOR PCIE 100MHz
PG 8,9 NBGFX_CLK
LAYER 4 : IN2
DDR II 667 MHZ
D
Griffin Processor ICS9LPRS476AKLFT
LAYER 5 : VCC D
USB 48MHz
NBGPP_CLK LAYER 6 : BOT
DDRII-SODIMM2 SLG8SP628VTR
REF 14MHz
PG 8,9 SBLINK_CLK
PG 3
(638 S1g2 socket)
Daughter Board
PG 4,5,6,7
MMB Board
LVDS HT_LINK
LVDS RTL8102EL(10/100) RJ45
PCI-E, 1X (port2)
PG 19 PG 23 PG 23
LVDS(2ch)
PCI-E, 1X (port0) USB Board
DVI USB2.0 (P3) Mini Card (WLAN)
CRT RX781/RS780MC PG 24
PG 18
PG 18 PCI-E, 1X (port1)
Touch Pad board
21mm X 21mm, 528pin BGA
USB2.0 (P8) Mini Card (TV)
PG 24
MXM Module PCI-E X16
PCI-E, 1X (port3)
PG 20 USB2.0 (P10) NEW CARD Switch board
C
HDMI PG 24 C
PG 18 PG 10,11,12,13 PCI-E, 1X (port4) Card Reader
JMB380 PG 25 4 IN 1 PG 25
A_LINK (X4)
IEEE1394 CN.PG 25
SBSRC_CLK CPU_CORE1
SATA - HDD1 SATA0 CPU_CORE2
USB2.0 (P7) CPU VDDNB_CORE CPU CORE
PG 26 USB2.0 I/O Ports X1
SB700 (MB) PG 27
NB_CORE NB CORE
SATA - HDD2 SATA1 USB2.0 (P0) USB2.0 I/O Ports X1 (1.0~1.1V)
USB2.0 (P2)
CCD (DB) PG 27
PG 26 PG 27
USB2.0 (P1) USB2.0 I/O Ports X1
USB2.0 (P9) (DB) PG 27 RVCC1.2
SATA - ODD SATA2 RVCC1.2
Bluetooth USB2.0 (P6) VCC1.2
PG 26 PG 27 USB2.0 I/O Ports X1
B
(DB) PG 27 B
21mm X 21mm, 528pin BGA
E - SATA SATA3 Azalia 1.8VSUS
Azalia Audio Codec 1.8VSUS
4.5W(Ext)
PG 27 VCC1.8 SMDDR
4.3W(Int) ALC272/ALC268
PG 21 SMDDR_VTERM VTERM
VCC1.5
PORT-A
PORT-B
Flash 1.1V_NB
PG 14,15,16,17,18
PG 26 Speaker Amplifier
G1441 3VPCU
LPC PG 21 RVCC3 3V/5V
3VSUS
VCC3
5VPCU
EC H.P/ MIC INT. INT. WOOFER
5VSUS
JACK JACK MIC S.P.
IT8512 VCC5
PG 22 PG 22 PG 22 PG 21 PG 22
A PG 28 VCC2.5 A
SPI
PROJECT : PF1
Flash Touch
FAN Keyboard CIR Quanta Computer Inc.
ROM Pad
Size Document Number Rev
PG 6 PG 29 PG 28 PG 27 PG 28 BLOCK DIAGRAM 2A
Date: Wednesday, June 11, 2008 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1
02
PF1 Power On Sequence BOM naming rule
From AC,Battery VIN
Items Function BTO Name Description
5VPCU 3VPCU
D From PWM SYS_HWPG(PCU) 1 UMA v IV@ Internal VGA stuff D
From Power Button NBSWON# 2 Discrete VGA v EV@ External VGA stuff
From EC RVCC_ON
3 Subwoofer v WF@ Only for PF2P
RVCC5
4 IEEE 1394 v EV@ External VGA model stuff
RVCC3
RVCC1.2 5 DVI-I v EV@ External VGA model stuff
>10ms
From EC RSMRST# >100ms 6 D-SUB(CRT) v IV@ Internal VGA model stuff
From EC DNBSWON#
7 HDMI v EV@ External VGA model stuff
From SB PCIE_WAKE#
From SB to EC SUSB#,SUSC# SUSON 8 CIR v CIR@ For PF1P and PF2P(M86)
From EC SUSON 9 TV TV@ For PF1P and PF2P(M86)
3VSUS 1.8VSUS SMDDR_VREF SMDDR_VTERM
10
From PWM HWPG_1.8V (SUS) MAINON
From EC MAINON 11
C C
VCC5 VCC3 VCC2.5 VCC1.8 VCC1.5 NB_CORE 1.1V_NB 12
From PWM HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN) HWPG_1.2_NB
13
From EC VRON
CPU_CORE0, CPU_CORE1, CPU VDDNB_CORE, VCC1.2 14
From PWM VRM_PWRGD (CPU) 15
HWPG 16
From EC ECPWROK
17
SB_PWRGD 0ns~30ns
NB_PWRGD 99ms~108ms
18
From SB CPU_PWRGD/LDT_PG 19
From SB PLTRST# PCIRST#
20
From SB CPU_LDT_RST#
From SB CPU_LDT_STOP# 21
B B
22
23
24
25
*Note: EC will sampling SUSB# & EC SMBUS Table
SUSC# every 5ms. Battery CPU thermal Sensor EC EEPROM VGA thermal Sensor Touch Sensor HDMI CEC
AMD SB700 SMBUS Table EC775 SDATA1/SCLK1(3VPCU) V
CLK GEN RAM Mini Card (TV) Mini-card(WL) New Card HDMI EC775 SDATA2/SCLK2(3VPCU) V V
SB700 SDATA0/SCLK0(VCC3) V V V V V EC775 SDATA3/SCLK3(3VPCU) V V V
A
SB700 SDATA1/SCLK1(3V_S5) V EC775 SDATA4/SCLK4(3VPCU) A
SB700 SDATA2/SCLK2(3V_S5) Power 3VPCU VCC3 3VPCU VCC3 3VPCU 5VPCU
Power VCC3 VCC3 VCC3 VCC3(Atheros) VCC3 RVCC3 Reserve MOS ckt X V X V X V
Reserve MOS ckt V V V V V V
PROJECT : PF1
Quanta Computer Inc.
Size Document Number Rev
SYSTEM INFORMATION 2A
Date: Wednesday, June 11, 2008 Sheet 2 of 40
5 4 3 2 1
5 4 3 2 1
CLK_GEN_SLG8SP628 03
VCC3 CLK_VDD VCC1.2 CLK_VDDIO
L29 L30
BK1608HS600 BK1608HS600
C259 C272 C313 C296 C307 C312 C290 C277 C273 C301 C260 C289 C258
C266 C267
D 22U/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 22U/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 D
ICS9LPRS480 P/N : ALPRS480000 Clock chip has internal serial terminations
for differencial pairs, external resistors are
SLG8SP628 P/N : AL8SP628000 reserved for debug purpose.
RTM880N-796 P/N : AL000880000
Place within 0.5"
of CLKGEN R221
U4
*261/F_4
4 50 CPUCLKP_R RP39 1 2 0X2 CPUCLKP
VCC3 CLK_VDD_USB CLK_VDD VDDDOT CPUK8_0T CPUCLKP (4)
16 49 CPUCLKN_R 3 4 CPUCLKN To CPU
VDDSRC CPUK8_0C CPUCLKN (4)
L33 26 VDDATIG
35 VDDSB_SRC RS780/RX781 for VGA
BK1608HS600 40 30 NBGFX_CLKP_R RP30 1 2 0X2 NBGFX_CLKP
VDDSATA ATIG0T NBGFX_CLKP (11)
1
48 29 NBGFX_CLKN_R 3 4 NBGFX_CLKN To NB
VDDCPU ATIG0C NBGFX_CLKN (11)
C310 55 28 MXM_REFCLKP_R RP31 1 2 EV@0X2 MXM_REFCLKP
VDDHTT ATIG1T MXM_REFCLKP (20)
10/25 modify it 2.2U/6.3V_6 56 27 MXM_REFCLKN_R 3 4 MXM_REFCLKN
MXM_REFCLKN (20)
2
VDDREF ATIG1C
63 VDD48
C 37 SBLINK_CLKP_R RP35 1 2 0X2 SBLINK_CLKP C
SB_SRC0T SBLINK_CLKP (11)
11 36 SBLINK_CLKN_R 3 4 SBLINK_CLKN To NB
CLK_VDDIO VDDSRC_IO0 SB_SRC0C SBLINK_CLKN (11)
VCC3 17 32 SBSRC_CLKP_R RP29 1 2 0X2 SBSRC_CLKP 11/4 check RX781
VDDSRC_IO1 SB_SRC1T SBSRC_CLKP (13)
25 31 SBSRC_CLKN_R 3 4 SBSRC_CLKN To SB
VDDATIG_IO SB_SRC1C SBSRC_CLKN (13)
34 VDDSB_SRC_IO
Q16 47 RX781 only
R189 *RHU002N06 VDDCPU_IO NBGPP_CLKP_R RP32 EV@0X2 NBGPP_CLKP
SRC0T 22 1 2 NBGPP_CLKP (11)
2
21 NBGPP_CLKN_R 3 4 NBGPP_CLKN To NB
SRC0C NBGPP_CLKN (11)
*10K_4 1 20 CLK_PCIE_NEW_R RP33 1 2 0X2 CLK_PCIE_NEW
GND48 SRC1T CLK_PCIE_NEW (24)
CLKREQ4# 1 3 7 19 CLK_PCIE_NEW#_R 3 4 CLK_PCIE_NEW# To New Card
CLKREQ_LAN# (23) GNDDOT SRC1C CLK_PCIE_NEW# (24)
10 15 CLK_PCIE_MINI_R RP34 1 2 0X2 CLK_PCIE_WLAN
GNDSRC0 SRC2T CLK_PCIE_WLAN (24)
18 14 CLK_PCIE_MINI#_R 3 4 CLK_PCIE_WLAN# To Mini PCIE Slot
GNDSRC1 SRC2C CLK_PCIE_WLAN# (24)
CLK_PCIE_MINI2_R RP36 0X2 CLK_PCIE_MINICARD
24
33
GNDATIG QFN64 SRC3T 13
12 CLK_PCIE_MINI2#_R
1
3
2
4 CLK_PCIE_MINICARD#
CLK_PCIE_MINICARD (24)
To Mini PCIE Slot
GNDSB_SRC SRC3C CLK_PCIE_MINICARD# (24)
VCC3 43 9 CLK_PCIE_LAN_R RP37 1 2 0X2 CLK_PCIE_LAN
GNDSATA SRC4T CLK_PCIE_LAN (23)
46 8 CLK_PCIE_LAN#_R 3 4 CLK_PCIE_LAN# To LAN Controller
GNDCPU SRC4C CLK_PCIE_LAN# (23)
52 GNDHTT
Q17 60
R201 *RHU002N06 GNDREF CLK_PCIE_JM380_R RP38 CLK_PCIE_JM380
SRC6T/SATAT 42 1 2 0X2 CLK_PCIE_JM380 (25)
2
41 CLK_PCIE_JM380#_R 3 4 CLK_PCIE_JM380# To 4 in 1 Controller
SRC6C/SATAC CLK_PCIE_JM380# (25)
*10K_4 CG_XIN 61 6 T89
CLKREQ2# CG_XOUT X1 SRC7T/27M_SS
1 3 CLKREQ_WLAN# (24) 62 X2 SRC7C/27M_NS 5 T91
B:(10/25) Add WLAN & LAN CLKREQ circuit (BOI request) 2 54 NBHT_REFCLKP_R RP40 1 2 0X2 NBHT_REFCLKP
(7,8,14,24) PCLK_SMB SMBCLK HTT0T/66M NBHT_REFCLKP (11)
3 53 NBHT_REFCLKN_R 3 4 NBHT_REFCLKN To NB
(7,8,14,24) PDAT_SMB SMBDAT HTT0C/66M NBHT_REFCLKN (11)
CLK_PD# 51 64 CLK_48M_USB_R R207 33_4 CLK_48M_USB To SB
PD# 48MHz_0 CLK_48M_USB (14)
T58 23 59 SEL_HTT66
B New Card CLKREQ# NEW_CLKREQ# CLKREQ0# REF0/SEL_HTT66 SEL_SATA B
(24) NEW_CLKREQ# 45 CLKREQ1# REF1/SEL_SATA 58 Ra
CLKREQ2# 44 57 SEL_27 R224 158/F_4 EXT_NB_OSC To NB
CLKREQ2# REF2/SEL_27 EXT_NB_OSC (11)
T85 39 R225 90.9/F_4
CLKREQ4# CLKREQ3#
38 CLKREQ4#
Rb NB CLOCK INPUT TABLE
TGND0
TGND1
TGND2
TGND3
TGND4
TGND5
TGND6
TGND7
TGND8
TGND9
C321 C306 NB CLOCKS RX781 RS780
*10P_4 *10P_4 RX780 RS780
SLG8SP628 HT_REFCLKP 100M DIFF 100M DIFF
65
66
67
68
69
70
71
72
73
74
C316 30P CG_XIN 1.8V 1.1V
HT_REFCLKN 100M DIFF 100M DIFF
2
CLK_VDD
Y3 Ra 82.5R 158R REFCLK_P 14M SE (1.8V) 14M SE (1.1V)
R202 8.2K_4 NEW_CLKREQ# 14.318MHZ/20P 10/17 Add 10p for EMI issue (Suggestion by Seligo)
R213 8.2K_4 CLK_PD# REFCLK_N NC vref
1
CG_XOUT Rb 130R 90.9R
C315 30P GFX_REFCLK 100M DIFF 100M DIFF(IN/OUT)*
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