Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_BD9
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5 4 3 2 1
PCB STACK UP
LAYER 1 : TOP
LAYER 2 : GND BD9 FT3 Kabini Block Diagram 01
LAYER 3 : IN1
LAYER 4 : SVCC
DDRIII-SODIMM1
LAYER 5 : IN2 DDRIII-SODIMM2
D Page 10,11 LVDS CONN D
LAYER 6 : IN3 Single Channel DDR III Port 0
RTD2136R LVDS Panel
LAYER 7 : GND Page 24 Page 30
800~1866 MHZ
LAYER 8 : BOT X'TAL
APU For support PRD 1600x900
25MHz
Atheros LVDS CONN
10/100M PCIe-0 PCI-Express eDP Panel
Transformer AR8162B Kabini APU 25W/15W Page 30
Page 26
Page 26
SoC
WLAN Con. PCIe-1 Port 1
RJ45 HDMI CONN
Page 26 Page 25
Page 28
24.5mm X 24.5mm POWER SYSTEM
ISL88732 P34
SATA - HDD Con. SATA 0 SATA
BGA 769 pin TPS51123A P35
C Page 31
PCI-E x4 dGPU TPS51216RUKR P36 C
VRAM DDR3-256MB*4 TPS51211DSCR P37
GFX Mars/Sun VRAM DDRIII
SATA - ODD Con. SATA 1 VRAM DDR3-512MB*4 ISL62771 P38
Pro Page 20, 21 P39
Support zero power ODD Discharge
Page 31 29mm X 29mm ISL62881CHRTZ-T P40
Page 12~19,22
G9661-25ADJF12U P41
USB2_0 USB 2.0 (Port 0 ~ 9) X'TAL
USB/B USB2.0 USB3.0 27.0MHz
Page 23
CHARGER P34
USB 3.0 (Port 0 ~ 1) USB3_0
USB2_1
USB/B USB2_8 USB3.0 w/ S&C +15V
Page 23 +3VPCU
X'TAL Page 23
32.768KHz
USB3_1 +3V_S5
Genesys Logic USB2_5 +3V
Card Reader Con.
Page 29 GL834L Page 29 USB2_9 USB3.0 w/o S&C +5VPCU
Page 23 +5V_S5
USB2_6 X'TAL +5V P35
48 MHz
CCD +1.5V_RTC
Page 30
+SMDDR_VTERM
B
BATTERY +SMDDR_VREF B
USB2_7
WLAN +1.5VSUS
SPI
Page 28 +1.5V_S5
Azalia IHDA +1.5V P36
SPI
Page 8 +0.95V_DUAL
LPC +0.95V
SPI +1.8V_S5
+1.8V P37
Conexant Nuvoton
Audio Codec EC NPCE985L +VDD_CORE
Page 33
CX20756-11Z Page 27 +VDDNB_CORE
P38
Port-B
Port-A
FAN HALL Sensor LED K/B Con. Touch Pad /B Power /B DISCHARGE P39
Con. Con.
MIC JACK HP SPK Con. Page 7 Page 30 Page 29 Page 32 Page 32 Page 32
Page 27 Page 27 Page 27 +VGPU_CORE P40
A A
+1.8V_GPU
+1.5V_GPU
+0.95V_GPU P41
Quanta Computer Inc.
PROJECT : BD9
Size Document Number Rev
Block Diagram A1A
Date: Tuesday, December 25, 2012 Sheet 1 of 41
5 4 3 2 1
5 4 3 2 1
02
Table of Contents
PAGE DESCRIPTION BOI-FUNCTION Power States
D CONTROL D
POWER PLANE VOLTAGE SIGNAL ACTIVE IN
1 Schematic Block Diagram
2 Power Stage
VIN 10V~+19V S0~S5
3-8 Processor CPU
9 Straps CPU +VCCRTC +1.5V S0~S5
10 SO-DIMM 1 DDR
+3V +3.3V MAIND S0
11 SO-DIMM 2 DDR
12 - 19 Mars/Sun Pro(M2) VGA +3V_S5 +3.3V S5_ON S0~S5
20 - 21 VRAM - DDR3 VGA
+3VPCU +3.3V AC/DC Insert enable S0~S5
22 PX5 VGA
23 USB U3B/USB +5V +5V MAIND S0
24 eDP to LVDS(RTD2136R) LDS
+5V_S5 +5V S5_ON S0~S5
25 HDMI/Touch Screen HDM/TSN
26 LAN(1AR8162B) LAN +5VPCU +5V AC/DC Insert enable S0~S5
27 Codec (CX20756-11Z) ADO
28 MINI CARD (WLAN) MNW +WIMAX_P +3.3V IOAC_EN S0
29 CARD READER(GL834L)/LED MMC/LED
+1.5VSUS +1.5V SUSON S0~S3
30 LDS/CRT/CCD LDS/CRT/CCD
31 HDD/ODD HDD/ODD +1.5V +1.5V MAIND S0
C C
32 KB/TouchPad KBC/TPD
+1.8V_S5 +1.8V PE_PWRGD ^ PE_GPIO1 S0~S5
33 EC 985L KBC
34 Charger (ISL88731CHRTZ-T) CHR +0.95V_DUAL +0.95V +0.95V_DUAL_EN S0~S5
35 System 5V/3V PWM
36 DDR 1.5V PWM +0.95V +0.95V MAIND S0
37 +0.95V_DUAL PWM
38 +VCC_CORE PWM +VDD_CORE ~ VRON S0
39 Discharge PWM
+VDDNB_CORE ~ VRON S0
40 GPU_CORE PWM
41 +0.95V_GPU/+1.8V_GPU/+1.5V_GPU/+3V_GPU PWM +VGPU_CORE GPU_MAINON ^ PE_GPIO1 S0
+1.8V_GPU +1.8V GPU_MAIND S0
+0.95V_GPU +0.95V GPU_MAINON ^ PE_GPIO1 S0
+3V_GPU +3.3V GPU_MAIND S0
+1.5V_GPU +1.5V GPU_MAIND S0
GND PLANE PAGE
B GND_SIGNAL B
8769GND
GND ALL
ADOGND
A A
Quanta Computer Inc.
PROJECT : BD9
Size Document Number Rev
A1A
POWER STAGE & BOI-FUNCTION
Date: Tuesday, December 25, 2012 Sheet 2 of 41
5 4 3 2 1
5 4 3 2 1
U22B
PCIE
Coupling Caps Note:
X5R is required. 03
PCIE_RXP_LAN R10 P_GPP_RXP0 P_GPP_TXP0 L2 PCIE_TXP_LAN_C C624 [email protected]/10V_4X PCIE_TXP_LAN
[26] PCIE_RXP_LAN PCIE_TXP_LAN [26]
PCIE_RXN_LAN R8 L1 PCIE_TXN_LAN_C C621 [email protected]/10V_4X PCIE_TXN_LAN
PCIe-LAN [26] PCIE_RXN_LAN
P_GPP_RXN0 P_GPP_TXN0
PCIE_TXN_LAN [26] PCIe-LAN
D PCIE_RXP_WLAN R5 K2 PCIE_TXP_WLAN_C C622 0.1U/10V_4X PCIE_TXP_WLAN D
P_GPP_RXP1 P_GPP_TXP1
[28] PCIE_RXP_WLAN R4 K1 PCIE_TXP_WLAN [28]
PCIE_RXN_WLAN PCIE_TXN_WLAN_C C620 0.1U/10V_4X PCIE_TXN_WLAN
PCIe-WLAN [28] PCIE_RXN_WLAN
P_GPP_RXN1 P_GPP_TXN1
PCIE_TXN_WLAN [28] PCIe-WLAN
N5 P_GPP_RXP2 P_GPP_TXP2 J2
N4 P_GPP_RXN2 P_GPP_TXN2 J1
N10 P_GPP_RXP3 P_GPP_TXP3 H2
N8 P_GPP_RXN3 P_GPP_TXN3 H1
R109 1.69K/F_4 P_TX_ZVDD W8 P_TX_ZVDD_095 P_RX_ZVDD_095 W7 P_RX_ZVDD R104 1K/F_4
+0.95V +0.95V
PEG_RXP0 L5 P_GFX_RXP0 P_GFX_TXP0 G2 PEG_TXP0_C C619 [email protected]/10V_4X PEG_TXP0
[12] PEG_RXP0 L4 G1 PEG_TXP0 [12]
PEG_RXN0 P_GFX_RXN0 P_GFX_TXN0 PEG_TXN0_C C617 [email protected]/10V_4X PEG_TXN0
[12] PEG_RXN0 PEG_TXN0 [12]
PEG X 4
PEG_RXP1 J5 P_GFX_RXP1 P_GFX_TXP1 F2 PEG_TXP1_C C618 [email protected]/10V_4X PEG_TXP1
[12] PEG_RXP1 J4 F1 PEG_TXP1 [12]
PEG_RXN1 P_GFX_RXN1 P_GFX_TXN1 PEG_TXN1_C C616 [email protected]/10V_4X PEG_TXN1
[12] PEG_RXN1 PEG_TXN1 [12]
PEG_RXP2 G5 P_GFX_RXP2 P_GFX_TXP2 E2 PEG_TXP2_C C615 [email protected]/10V_4X PEG_TXP2
[12] PEG_RXP2 PEG_TXP2 [12]
PEG_RXN2 G4 P_GFX_RXN2 P_GFX_TXN2 E1 PEG_TXN2_C C613 [email protected]/10V_4X PEG_TXN2
[12] PEG_RXN2 PEG_TXN2 [12]
PEG_RXP3 D7 P_GFX_RXP3 P_GFX_TXP3 D2 PEG_TXP3_C C614 [email protected]/10V_4X PEG_TXP3
[12] PEG_RXP3 PEG_TXP3 [12]
PEG_RXN3 E7 P_GFX_RXN3 P_GFX_TXN3 D1 PEG_TXN3_C C612 [email protected]/10V_4X PEG_TXN3
C [12] PEG_RXN3 PEG_TXN3 [12] C
FT3 REV 0.53
FT3
+1.8V
HDT+ Connector
+1.8V SPEC X with CHECK LIST
J1
R41 1 2 APU_TCK
CPU_VDDIO1 CPU_TCK APU_TCK [5]
*DEBUG@1K_4 3 4 APU_TMS
5 GND1 CPU_TMS 6 APU_TMS [5]
APU_TDI
7 GND2 CPU_TDI 8 APU_TDI [5]
APU_TDO
GND3 CPU_TDO APU_TDO [5]
APU_TRST# R47 DEBUG@0_4 9 10 APU_PWROK_BUF
[5] APU_TRST# 11 CPU_TRST_L CPU_PWROK_BUF 12
R53 DEBUG@10K_4 APU_RST_L_BUF
R55 DEBUG@10K_4 13 CPU_DBRDY3 CPU_RST_L_BUF 14 APU_DBRDY
15 CPU_DBRDY2 CPU_DBRDY0 16 APU_DBRDY [5]
R62 DEBUG@10K_4 DBREQ# R64 *DEBUG/EVB@0_4 APU_DBREQ#
17 CPU_DBRDY1 CPU_DBREQ_L 18 APU_DBREQ# [5]
B APU_TEST19_PLLTEST0 B
GND4 CPU_PLLTEST0 APU_TEST19_PLLTEST0 [5]
19 20 APU_TEST18_PLLTEST1
CPU_VDDIO2 CPU_PLLTEST1 APU_TEST18_PLLTEST1 [5]
*DEBUG@HDT+ HEADER
Debug only
R600 *0_4
C26 *E@1000P/50V_4X Close by HDT+ Conector
APU_TDI R387 *DEBUG@1K_4
Debug only APU_TCK R389 *DEBUG@1K_4
+1.8V
U3 APU_TMS R388 *DEBUG@1K_4
APU_RST# 1 6 APU_RST_L_BUF R28 *DEBUG@1K_4 +1.8V APU_DBREQ# R69 *DEBUG@1K_4
[5] APU_RST# A1 Y1
2 5 +1.8V C44
GND VCC
APU_PWRGD 3 4 APU_PWROK_BUF R25 *DEBUG@1K_4 *[email protected]/10V_4X
[5] APU_PWRGD A2 Y2
C21 *DEBUG@74LVC2G07
A *[email protected]/10V_4X C23 C20 A
*[email protected]/10V_4X *E@1000P/50V_4X
R601 *0_4
Quanta Computer Inc.
PROJECT : BD9
RevB 1221 Add 0 ohm for debug Size Document Number Rev
A1A
APU 1/6(PCIE/GPP)
Date: Tuesday, December 25, 2012 Sheet 3 of 41
5 4 3 2 1
5 4 3 2 1
04
U22A
M_A_A[15:0] MEMORY M_A_DQ[63:0]
[10,11] M_A_A[15:0] M_A_DQ[63:0] [10,11]
M_A_A0 AG38 M_ADD0 M_DATA0 B30 M_A_DQ0
D M_A_A1 W 35 M_ADD1 M_DATA1 A32 M_A_DQ1 D
M_A_A2 W 38 M_ADD2 M_DATA2 B35 M_A_DQ2
M_A_A3 W 34 M_ADD3 M_DATA3 A36 M_A_DQ3
M_A_A4 U38 M_ADD4 M_DATA4 B29 M_A_DQ4
M_A_A5 U37 M_ADD5 M_DATA5 A30 M_A_DQ5
M_A_A6 U34 M_ADD6 M_DATA6 A34 M_A_DQ6
M_A_A7 R35 M_ADD7 M_DATA7 B34 M_A_DQ7
M_A_A8 R38 M_ADD8
M_A_A9 N38 M_ADD9 M_DATA8 B37 M_A_DQ8
M_A_A10 AG34 M_ADD10 M_DATA9 A38 M_A_DQ9
M_A_A11 R34 M_ADD11 M_DATA10 D40 M_A_DQ10
M_A_A12 N37 M_ADD12 M_DATA11 D41 M_A_DQ11
M_A_A13 AN34 M_ADD13 M_DATA12 B36 M_A_DQ12
M_A_A14 L38 M_ADD14 M_DATA13 A37 M_A_DQ13
M_A_BS#[2:0] M_A_A15 L35 M_ADD15 M_DATA14 B41 M_A_DQ14
[10,11] M_A_BS#[2..0] C40
M_DATA15 M_A_DQ15
M_A_BS#0 AJ38 M_BANK0
M_A_BS#1 AG35 M_BANK1 M_DATA16 F40 M_A_DQ16
M_A_DM[7:0] M_A_BS#2 N34 M_BANK2 M_DATA17 F41 M_A_DQ17
[10,11] M_A_DM[7..0] K40
M_DATA18 M_A_DQ18
M_A_DM0 B32 M_DM0 M_DATA19 K41 M_A_DQ19
M_A_DM1 B38 M_DM1 M_DATA20 E40 M_A_DQ20
M_A_DM2 G40 M_DM2 M_DATA21 E41 M_A_DQ21
M_A_DM3 N41 M_DM3 M_DATA22 J40 M_A_DQ22
M_A_DM4 AG40 M_DM4 M_DATA23 J41 M_A_DQ23
M_A_DM5 AN41 M_DM5
M_A_DM6 AY40 M_DM6 M_DATA24 M41 M_A_DQ24
M_A_DM7 AY34 M_DM7 M_DATA25 N40 M_A_DQ25
TP40 Y40 M_DM8 M_DATA26 T41 M_A_DQ26
M_DATA27 U40 M_A_DQ27
C M_A_DQSP0 B33 M_DQS_H0 M_DATA28 L40 M_A_DQ28 C
[10,11] M_A_DQSP0
M_A_DQSN0 A33 M_DQS_L0 M_DATA29 M40 M_A_DQ29
[10,11] M_A_DQSN0 M_A_DQSP1 B40 R40 M_A_DQ30
M_DQS_H1 M_DATA30
[10,11] M_A_DQSP1
M_A_DQSN1 A40 M_DQS_L1 M_DATA31 T40 M_A_DQ31
[10,11] M_A_DQSN1 H41
M_A_DQSP2 M_DQS_H2
[10,11] M_A_DQSP2 H40 AF40
M_A_DQSN2 M_DQS_L2 M_DATA32 M_A_DQ32
[10,11] M_A_DQSN2
M_A_DQSP3 P41 M_DQS_H3 M_DATA33 AF41 M_A_DQ33
[10,11] M_A_DQSP3 P40 AK40
M_A_DQSN3 M_DQS_L3 M_DATA34 M_A_DQ34
[10,11] M_A_DQSN3
M_A_DQSP4 AH41 M_DQS_H4 M_DATA35 AK41 M_A_DQ35
[10,11] M_A_DQSP4
M_A_DQSN4 AH40 M_DQS_L4 M_DATA36 AE40 M_A_DQ36
[10,11] M_A_DQSN4 AP41 AE41
M_A_DQSP5 M_DQS_H5 M_DATA37 M_A_DQ37
[10,11] M_A_DQSP5 AP40 AJ40
M_A_DQSN5 M_DQS_L5 M_DATA38 M_A_DQ38
[10,11] M_A_DQSN5 M_A_DQSP6 BA40 AJ41 M_A_DQ39
M_DQS_H6 M_DATA39
[10,11] M_A_DQSP6
M_A_DQSN6 AY41 M_DQS_L6
[10,11] M_A_DQSN6 AY33 AM41
M_A_DQSP7 M_DQS_H7 M_DATA40 M_A_DQ40
[10,11] M_A_DQSP7 M_A_DQSN7 BA34 AN40 M_A_DQ41
M_DQS_L7 M_DATA41
[10,11] M_A_DQSN7
AA40 M_DQS_H8 M_DATA42 AT41 M_A_DQ42
Y41 M_DQS_L8 M_DATA43 AU40 M_A_DQ43
M_DATA44 AL40 M_A_DQ44
M_A_CLKP0 AC35 M_CLK_H0 M_DATA45 AM40 M_A_DQ45
[10] M_A_CLKP0 AC34 AR40
M_A_CLKN0 M_CLK_L0 M_DATA46 M_A_DQ46
+1.5VSUS [10] M_A_CLKN0 AA34 AT40
M_A_CLKP1 M_CLK_H1 M_DATA47 M_A_DQ47
[10] M_A_CLKP1 AA32
M_A_CLKN1 M_CLK_L1
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