Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_BY7
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5 4 3 2 1
PCB STACK UP
14" BY7 Brazos 2.0 Block Diagram 01
LAYER 1 : TOP
LAYER 2 : GND UMA DISCRETE
AMD FUSION APU
INT_HDMI
LAYER 3 : IN1 Zacate/Ontario EXT_HDMI
D HDMI PG 19 D
LAYER 4 : SVCC
413-BALL INT_LVDS
LAYER 5 : IN2 DDRIII-SODIMM2 DDRIII-SODIMM1 EXT_LVDS
LVDS PG 21
PG 11 PG 10 19mmX19mm BGA
LAYER 6 : IN3
INT_CRT
LAYER 7 : GND EXT_CRT
CRT PG 21
SINGLE CHANNEL DDR3
LAYER 8 : BOT
DISPLAY PORT X2
DX11 IGP
4 X1 PCIE GEN2 GPP
1 X4 UMI-LINK GEN1
VGA DAC Graphics
PCI-E X4
Thames LE VRAM DDR3
PG 2,3,4
PAGE 19
29mm X 29mm
PG 12,13,14,15,16,17,18
VGA AMD Thames LE
X'TAL
27.0MHz
C UMI LINK POWER SYSTEM
DP1(x4) 2.5GT /s ISL88731CHRTZ-T P36
C
RT8223P P37
UMI(x4) TPS51216RUKR P38
TPS51211DSCR P39
DMI TPS51211DSCR P40
SATA - HDD Con. SATA 0 USB 2.0 (Port0~13) USB2-0 USB2.0 Con.
USB2.0 TPS51211DSCR P40
P33 P25
OZ8380ALN P41
SATA
USB2-5 ISL95870AHRUZ P42
SATA - ODD Con. SATA 1 Card Reader 3 IN 1
P33 Card Reader Con.
(AU6437B53-GDL-GR) P31 P31
P36
PCI-E, 1X (port2) CHARGER
RJ45 AR8152(10/100) PCIE USB2-6 CCD
PG 26 PG 26 P32 +15V P37
AMD
PCI-E, 1X (port0) +3VPCU
Mini Card I (WIFI) Hudson M3L USB 3.0 (Port0~3) USB3-0
PG 22 USB2.0 (P7) USB3.0 +3V_S5
USB2-10 USB3.0 Con. +3V
P25 +3V_GPU
FCH +5VPCU
USB3-1 +5V_S5
BATTERY RTC 24.5mm X 24.5mm USB3.0 re-driver IC
B
P8 P25 +5V B
X'TAL
32.768KHz DISCHARGE
LPC USB2-11 USB3.0 Con. +SMDDR_VTERM P38
P7, 8, 9, 10, 11
Azalia P25 +SMDDR_VREF
SPI IHDA
+1.5VSUS
+1.5V
+1.5V_GPU
SPI
P39
+1.0V
Share SPI flash +1.0V_GPU
PG 29
P40
Audio Codec CX20671-21Z +1.1V_S5
+1.1V
EC PG 25 +1.8V
+1.8V_GPU
PORT-A
PORT-B
NPCE885L
PG 29 P41
A CPU_CORE A
CPU_VDDNB_CORE
P42
MIC INT. +VGPU_CORE
FAN Keyboard Touch Pad LED Hall Sensor Touch Pad/B Power/B HP DMIC
JACK SPEAKER
PG 3 PG 28 PG 28 PG 31 PG 21 Con. PG 28 Con. PG 28 PG 25 PG 25 PG 25 PG 25 Quanta Computer Inc.
PROJECT : BY7
Size Document Number Rev
Block Diagram 1A
Date: Monday, December 12, 2011 Sheet 1 of 45
5 4 3 2 1
5 4 3 2 1
BOI
02
PAGE DESCRIPTION FUNCTIONS CONTROL Power States ITEM Value Code FUNCTIONS
POWER PLANE VOLTAGE SIGNAL ACTIVE IN 1 CEC@ CEC
1 Schematic Block Diagram
2 NMP@ LPC Debug Card
2 Front Page
VIN 10V~+19V S0~S5 3 512M@ VRAM 512M
3-5 Processor CPU
4 1GCA@ VRAM 1Gb*4(C-die, A-die)
D 6 - 10 FCH CLG +VCCRTC +3.0V~+3.3V S0~S5 D
5 1GEB@ VRAM 1Gb*4(E-die, B-die)
7 RTC RTC
+3V +3.3V MAINON S0 6 2G@ VRAM 2Gb
11 - 12 DDRIII SO-DIMM DDR
7 AMD@ AMD VRAM
13 - 20 Thames/Seymour(M2) VGA +3V_S5 +3.3V S5_ON S0~S5
8 Sam@ Samsung VRAM
21 - 22 VRAM - DDR3 VGA
+3VPCU +3.3V AC/DC Insert enable S0~S5 9 EV@ DISCRETE
23 RESERVE VGA
10 IV@ UMA
24 USB Connector USB +5V +5V MAINON S0
11 ECRT@ DISCRETE CRT
USB 3.0 Redriver U3B
+5V_S5 +5V S5_ON S0~S5 12 ICRT@ UMA CRT
USB Sleep Charger SLC
13 EHM@ DISCRETE HDMI
25 HDMI comm part HDM +5VPCU +5V AC/DC Insert enable S0~S5
14 IHM@ UMA HDMI
CEC CEC
WIMAX_P +3.3V WMAX_P S0 15 U3@ Internal USB 3.0
26 Atheros LAN LAN
16 U2@ USB 2.0 (colay W USB 3.0)
27 Codec (CX20671-21Z) ADO +1.8V +1.8V MAINON S0
17 ULD@ USB Port (Left Down)
28 MINI Card (Wi-Fi & WIMAX) MNW
+1.5VSUS +1.5V SUSON S0~S3 18 ULU@ USB Port (Left Up)
29 Card reader MMC
19 ULU2@ USB 2.0 Port (Left Up)
30 VGA Connector VGA +1.5V +1.5V MAINON S0
20 ULU3@ USB 3.0 Port (Left Up)
LCD Panel LDS
+1.1V_S5 +1.1V +1.1V_DUAL_EN S0~S5 21 UR@ USB Port (Right)
CRT & CRT BUS SWITCH CRT
22 UR2@ USB 2.0 Port (Right)
CCD CCD +1.1V +1.1V MAINON S0
C 23 UR3@ USB 300 Port (Right) C
HALL SENSOR&BACK LIGHT SWITCH HSR
+1V +1V MAINON S0
31 HDD HDD
ODD ODD CPU_CORE ~ VRON S0
32 Thermal THC
CPU_VDDNB_CORE ~ VRON S0
FAN THC
33 KeyBoard KBC +VGPU_CORE GPU_VRON S0
TP&FP board TPD,FPD
+1.8V_GPU +1.8V GPU_MAINON S0
Power SW PSW
34 EC NPCE885LA0DX KBC +1V_GPU +1V GFXPG_1V_EN S0
35 LED LED
+3V_GPU +3.3V GPU_MAINON S0
36 CHARGER-ISL88731C PWM
37 System 3V/5V(TPS51123A) PWM +1.5V_GPU +1.5V GPU_MAINON S0
38 DDR 1.5V PWM
39 +1.0V PWM
40 +1.1V/+1.8V PWM
41 CPU CORE PWM
42 GPU PWM
43 Power Tree
B 44 Power Sequence B
45 Change List
GND PLANE PAGE
8769GND 34
26
GND ALL
ADOGND 27
Shield_GND 27
A A
Quanta Computer Inc.
PROJECT : BY7
Size Document Number Rev
1A
POWER STAGE & BOI-FUNCTION
Date: Monday, December 12, 2011 Sheet 2 of 45
5 4 3 2 1
1 2 3 4 5 6 7 8
(11,12) M_A_A[15:0]
M_A_A0 R17
M_A_A1 H19
U5038E
M_ADD0
ONTARIO (2.0)
M_DATA0 B14 M_A_DQ0
M_A_DQ1
M_A_DQ[0..63] (11,12)
03
M_ADD1
PART 1 OF 5
M_DATA1 A15
M_A_A2 J17 M_ADD2 M_DATA2 A17 M_A_DQ2
M_A_A3 H18 M_ADD3 M_DATA3 D18 M_A_DQ3
M_A_A4 H17 M_ADD4 M_DATA4 A14 M_A_DQ4
M_A_A5 G17 M_ADD5 M_DATA5 C14 M_A_DQ5
M_A_A6 H15 M_ADD6 M_DATA6 C16 M_A_DQ6
M_A_A7 G18 M_ADD7 M_DATA7 D16 M_A_DQ7
M_A_A8 F19 M_ADD8
M_A_A9 E19 M_ADD9 M_DATA8 C18 M_A_DQ8
M_A_A10T19 M_ADD10 M_DATA9 A19 M_A_DQ9 PEG_TXN[3:0]
PEG_TXN[3:0] (13)
M_A_A11F17 M_ADD11 M_DATA10 B21 M_A_DQ10
M_A_A12E18 M_ADD12 M_DATA11 D20 M_A_DQ11 PEG_TXP[3:0]
A PEG_TXP[3:0] (13) A
M_A_A13
W17 M_ADD13 M_DATA12 A18 M_A_DQ12
M_A_A14E16 M_ADD14 M_DATA13 B18 M_A_DQ13 PEG_RXN[3:0]
PEG_RXN[3:0] (13)
M_A_A15G15 M_ADD15 M_DATA14 A21 M_A_DQ14
(11,12) M_A_BS#[2..0] PEG_RXP[3:0]
M_DATA15 C20 M_A_DQ15 PEG_RXP[3:0] (13)
M_A_BS#0
R18 M_BANK0
M_A_BS#1
T18 M_BANK1 M_DATA16 C23 M_A_DQ16
M_A_BS#2
F16 M_BANK2 M_DATA17 D23 M_A_DQ17 U5038A
(11,12) M_A_DM[7..0]
M_DATA18 F23 M_A_DQ18 PEG_RXP0 AA6 P_GPP_RXP0 P_GPP_TXP0 AB6 C_PEG_TXP0 C5562 [email protected]/10V_4X PEG_TXP0
M_A_DM0 D15 M_DM0 M_DATA19 F22 M_A_DQ19 PEG_RXN0 Y6 P_GPP_RXN0 P_GPP_TXN0 AC6 C_PEG_TXN0 C5563 [email protected]/10V_4X PEG_TXN0
M_A_DM1 B19 M_DM1 M_DATA20 C22 M_A_DQ20 ONTARIO (2.0)
M_A_DM2 D21 M_DM2 M_DATA21 D22 M_A_DQ21 PEG_RXP1 AB4 P_GPP_RXP1 PART 2 OF 5 P_GPP_TXP1 AB3 C_PEG_TXP1 C5564 [email protected]/10V_4X PEG_TXP1
M_A_DM3 H22 M_DM3 M_DATA22 F20 M_A_DQ22 PEG_RXN1 AC4 P_GPP_RXN1 P_GPP_TXN1 AC3 C_PEG_TXN1 C5565 [email protected]/10V_4X PEG_TXN1
M_A_DM4 P23 M_DM4 M_DATA23 F21 M_A_DQ23
M_A_DM5 V23 M_DM5 PEG_RXP2 AA1 P_GPP_RXP2 P_GPP_TXP2 Y1 C_PEG_TXP2 C5566 [email protected]/10V_4X PEG_TXP2
M_A_DM6
AB20 M_DM6 M_DATA24 H21 M_A_DQ24 PEG_RXN2 AA2 P_GPP_RXN2 P_GPP_TXN2 Y2 C_PEG_TXN2 C5567 [email protected]/10V_4X PEG_TXN2
PCIE I/F
M_A_DM7
AA16 M_DM7 M_DATA25 H23 M_A_DQ25
M_DATA26 K22 M_A_DQ26 VDD_10 PEG_RXP3 Y4 P_GPP_RXP3 P_GPP_TXP3 V3 C_PEG_TXP3 C5568 [email protected]/10V_4X PEG_TXP3
A16 M_DQS_H0 M_DATA27 K21 M_A_DQ27 PEG_RXN3 Y3 P_GPP_RXN3 P_GPP_TXN3 V4 C_PEG_TXN3 C5569 [email protected]/10V_4X PEG_TXN3
(11,12) M_A_DQSP0
B16 M_DQS_L0 M_DATA28 G23 M_A_DQ28
(11,12) M_A_DQSN0
B20 M_DQS_H1 M_DATA29 H20 M_A_DQ29 R9782 2K/F_4
ON_ZVDD Y14 P_ZVDD_10 P_ZVSS AA14 ON_ZVSS R9783 1.27K/F_4
(11,12) M_A_DQSP1
A20 M_DQS_L1 M_DATA30 K20 M_A_DQ30
(11,12) M_A_DQSN1
E23 M_DQS_H2 M_DATA31 K23 M_A_DQ31
(11,12) M_A_DQSP2
(11,12) M_A_DQSN2 E22 M_DQS_L2
MEMORY I/F
J22 M_DQS_H3 M_DATA32 N23 M_A_DQ32 (7) UMI_RXP0 AA12 P_UMI_RXP0 P_UMI_TXP0 AB12 UMI_TXP0_C C5570 0.1U/10V_4X UMI_TXP0 (7)
(11,12) M_A_DQSP3
J23 M_DQS_L3 M_DATA33 P21 M_A_DQ33 (7) UMI_RXN0 Y12 P_UMI_RXN0 P_UMI_TXN0 AC12 UMI_TXN0_C C5571 0.1U/10V_4X UMI_TXN0 (7)
(11,12) M_A_DQSN3
R22 M_DQS_H4 M_DATA34 T20 M_A_DQ34
(11,12) M_A_DQSP4
P22 M_DQS_L4 M_DATA35 T23 M_A_DQ35 (7) UMI_RXP1 AA10 P_UMI_RXP1 P_UMI_TXP1 AC11 UMI_TXP1_C C5572 0.1U/10V_4X UMI_TXP1 (7)
(11,12) M_A_DQSN4
W22 M20 M_A_DQ36 Y10 AB11 UMI_TXN1_C C5573 0.1U/10V_4X
UMI I/F
M_DQS_H5 M_DATA36 (7) UMI_RXN1 P_UMI_RXN1 P_UMI_TXN1 UMI_TXN1 (7)
(11,12) M_A_DQSP5
V22 M_DQS_L5 M_DATA37 P20 M_A_DQ37
(11,12) M_A_DQSN5
(11,12) M_A_DQSP6 AC20 M_DQS_H6 M_DATA38 R23 M_A_DQ38 (7) UMI_RXP2 AB10 P_UMI_RXP2 P_UMI_TXP2 AA8 UMI_TXP2_C C5574 0.1U/10V_4X UMI_TXP2 (7)
AC21 M_DQS_L6 M_DATA39 T22 M_A_DQ39 (7) UMI_RXN2 AC10 P_UMI_RXN2 P_UMI_TXN2 Y8 UMI_TXN2_C C5575 0.1U/10V_4X UMI_TXN2 (7)
(11,12) M_A_DQSN6
(11,12) M_A_DQSP7 AB16 M_DQS_H7
(11,12) M_A_DQSN7 AC16 M_DQS_L7 M_DATA40 V20 M_A_DQ40 (7) UMI_RXP3 AC7 P_UMI_RXP3 P_UMI_TXP3 AB8 UMI_TXP3_C C5576 0.1U/10V_4X UMI_TXP3 (7)
M_DATA41 V21 M_A_DQ41 (7) UMI_RXN3 AB7 P_UMI_RXN3 P_UMI_TXN3 AC8 UMI_TXN3_C C5577 0.1U/10V_4X UMI_TXN3 (7)
(12) M_A_CLKP0 M17 M_CLK_H0 M_DATA42 Y23 M_A_DQ42
(12) M_A_CLKN0 M16 M_CLK_L0 M_DATA43 Y22 M_A_DQ43 FT1_ONTARIO
(12) M_A_CLKP1 M19 M_CLK_H1 M_DATA44 T21 M_A_DQ44
(12) M_A_CLKN1 M18 M_CLK_L1 M_DATA45 U23 M_A_DQ45
(11) M_A_CLKP2 N18 M_CLK_H2 M_DATA46 W23 M_A_DQ46
B (11) M_A_CLKN2 N19 M_CLK_L2 M_DATA47 Y21 M_A_DQ47 B
+1.5VSUS
(11) M_A_CLKP3 L18 M_CLK_H3
(11) M_A_CLKN3 L17 M_CLK_L3 M_DATA48 Y20 M_A_DQ48
M_DATA49 AB22 M_A_DQ49
(11,12) M_A_RST# L23 M_RESET_L M_DATA50 AC19 M_A_DQ50
N17 M_EVENT_L M_DATA51 AA18 M_A_DQ51 +M_VREF R9784
(11,12) M_A_EVENT#
M_DATA52 AA23 M_A_DQ52 1K/F_4
M_DATA53 AA20 M_A_DQ53
(11,12) M_A_CKE0 F15 M_CKE0 M_DATA54 AB19 M_A_DQ54
(11,12) M_A_CKE1 E15 M_CKE1 M_DATA55 Y18 M_A_DQ55
M_DATA56 AC17 M_A_DQ56
M_DATA57 Y16 M_A_DQ57 R9786 C5578 C5579
W19 M0_ODT0 M_DATA58 AB14 M_A_DQ58 1K/F_4 M_A_EVENT# R9787 1K/F_4 +1.5VSUS
(12) M_A_ODT0
(12) M_A_ODT1 V15 M0_ODT1 M_DATA59 AC14 M_A_DQ59 0.1U/10V_4X 1000P/50V_4X
(11) M_A_ODT2 U19 M1_ODT0 M_DATA60 AC18 M_A_DQ60
(11) M_A_ODT3 W15 M1_ODT1 M_DATA61 AB18 M_A_DQ61
M_DATA62 AB15 M_A_DQ62
(12) M_A_CS#0 T17 M0_CS_L0 M_DATA63 AC15 M_A_DQ63
(12) M_A_CS#1 W16 M0_CS_L1
(11) M_A_CS#2 U17 M1_CS_L0
(11) M_A_CS#3 V16 M1_CS_L1 M_VREF M23 +M_VREF
(11,12) M_A_RAS# U18 M_RAS_L
(11,12) M_A_CAS# V19 M_CAS_L
V17 M_WE_L M_ZVDDIO_MEM_S M22 39.2/F_4 R9789 +1.5VSUS
(11,12) M_A_WE#
FT1_ONTARIO
C C
D D
Quanta Computer Inc.
PROJECT : BY7
Size Document Number Rev
1A
ONTARIO MEM & PCIE I/F(1/3)
Date: Monday, December 12, 2011 Sheet 3 of 45
1 2 3 4 5 6 7 8
1
CNTR_VREF
+1.8V
R9790
CNTR_VREF +3V
R9792
04
*20K/F_4
2
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