Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_GT1
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5 4 3 2 1
GT1 SYSTEM BLOCK DIAGRAM 1
FAN Driver
D Thersmal Sensor GMT CLOCK GEN D
GMT CPU CPU ICS
G995
G781 AMD ICS951462
(SO8) Page 26
(MSSOP-8) Athlon 2650(Single Core) 15W (64 Pin TSSOP)
DDRII 800
Page 6 Athlon x 2 3250(Dual Core) 22W Page 3
CPUCLKP,CPUCLKN
SO-DIMM NBSRC_CLKP,NBSRC_CLKN,SBLINK_CLKP,SBLINK_CLKN
Max. 2GB DDRII 800 AM2 SBSRCCLKP,SBSRCCLKN
Page 8~9
Page 4~7 CLK_PCIE_LAN,CLK_PCIE_LAN#
SO-DIMM HT_LINK 1
Max. 2GB LAN
Page 8~9 Transformer RJ45
PCIE0 Broadcom
Page 22 Page 22
BCM5784M
Thersmal Sensor (68 BGA)
GMT CPU North Bridge Page 22
AMD
C
G781 C
RS690MC PCIE1 CLK_PCIE_WLAN,CLK_PCIE_WLAN#
(MSSOP-8) Mini Card (WLAN)
USB8
Page 12 PCI Express
(BGA 465) Page 24
21 x 21 mm PCIE2 CLK_PCIE_TV,CLK_PCIE_TV#
18" LCD LVDS
24bit 1ch. 2 Lamp USB2 Mini Card (DTV)
Page 19 Page 10~13 PCI Express
Page 24
A-LINK (x4)
USB0,3,4,5,7,9 USB IO Port
HDD SATA0
Single*2 , Dual*2 (total 6)
2.5" , 9.5mm Page 27
Page 25
South Bridge
AMD WEBCAM + DMIC
ODD SATA1 USB6
SB600 2.5" , 9mm
NB Tray , 12.7mm Page 19
Page 25
B B
(BGA 594)
USB1 CIR OR BLUETOOTH
Card Reader Media Card/1394 23 x 23 mm
PCI
MS,SD RICOH Page 26/19
Page 21 Page 14~18
R5C833
(128 Pin TQFP) Headphone
1394 14 x 14 mm Page 20 LPC Audio Codec Page 23
Realtek
Page 20 Azallia
ALC269 MIC
EC (QFN64) Page 23
ITE 6 x 6 mm Page 23
ITE8502E Speaker
(128 Pin LQFP) 2W
Page 23
16 x 16 mm
Page 28
SPI
A A
BIOS ROM PS2
1MB
Page 28 Page 26
Quanta Computer Inc.
PROJECT : GT1
Size Document Number Rev
A
BLOCK DIAGRAM
Date: Sheet 1 of 36
5 4 3 2 1
5 4 3 2 1
Voltage Rails 2
Power Voltage S0~S2 S3 S4 S5 Ctl Signal
15VPCU 15V V V V V PCI DEVICES IRQ ROUTING
5VPCU 5V V V V V PCI DEVICE IDSEL# REQ# / GNT# Interrupts CLK
3VPCU 3V V V V V
D VCCRTC 3V V V V V NB(RS690) NA NA NA NA D
+3.3VALW 3V V V V V STB_ON_D SB(SB600) DEVSEL# REQ0#/GNT0# INTE# PCICLK0
+1.2VALW 1.2V V V V V STB_ON R5C833 IDSEL REQ#/GNT# INTA#/INTB# PCICLK
5VSUS 5V V V SUSON
V V SUSON
3VSUS 3V
1.8VSUS 1.8V V V SUSON
SMDDR_VTERM 0.9V V SUSON
VCC5 5V V MAINON
VCC3 3V V MAINON
VCC1.8 1.8V V MAINON
VCC1.5 1.5V V MAINON
VCC1.2 1.2V V MAINON
VLDT_RUN 1.2V V VLDT_ON_D
C C
CPU_VCCA 2.5V V MAINON
CPU_CORE 0.9V V VRON
Power On Sequence BONEFISH POWER UP SEQUENCE
ACIN +5VALW
5VPCU/3VPCU/15VPCU
RSMRST#
NBSWON#
PS_ON, SLP_S3#, SLP_S5#
PWRBTN#
+12V,5V,3.3V
RVCC_ON VDRM_PWRGD
B B
RSMRST# VCC_NB_PWRGD
SUSB#,SUSC# VRM_PWRGD
SUSON NB_PWRGD
MAINON SB_PWRGD
VSUS,VCC CPU_PWRGD
VR_ON PCI_RST#
PCB STACK UP CPU_CORE CPU_RST#
LAYER 1 : TOP NB_PWRGD T1 T2 T3
LAYER 2 : GND
T1>= 70 ms 1ms < T2 < 10ms
LAYER 3 : IN1 PWROK 1ms < T3 < 5ms
A LAYER 4 : IN2 A
LAYER 5 : VCC PCIRST#
LAYER 6 : BOT
Quanta Computer Inc.
PROJECT : GT1
Size Document Number Rev
A
System Infromation
Date: Thursday, April 09, 2009 Sheet 2 of 36
5 4 3 2 1
5 4 3 2 1
VCC3
VCC3 VCC3 VCC3
3
CLK_VDD VCC3
L422 BLM18AG221SN1D_6
L421 BK1608HS600 CLK_VDDA
R86 R574 R570
10K 10K 10K
C521 C203 C217 C523 C208 C207 C233 C223 C234 C533 C534
10U_0805 0.1U 0.1U 0.1U *0.1U 0.1U 0.1U 0.1U 0.1U 0.1U 10U_0805
D D
CLKREQ_WLAN# CLKREQ_LAN# CLKREQ_TV#
Put Decoupling Caps close to Clock Fen. power pin
VCC3
CLK_VDD
L11 BK1608HS600 CLK_VDD_USB U409
54 50 CLK_VDDA
C192 C202 VDDCPU VDDA R548 261/F
14 VDD_SRC1 GNDA 49
1U *0.1U 23 VDD_SRC2 CPUCLK_EXT_R R546 47.5/F
28 VDD_SRC3 CPUCLK8T0 56 CPUCLKP (6)
44 55 CPUCLK#_EXT_R R549 47.5/F
VCC3 VDD_SRC4 CPUCLK8C0 CPUCLKN (6)
5 VDD_48 CPUCLK8T1 52
39 VDD_ATIG CPUCLK8C1 51
L12 BK1608HS600 CLK_VDD_REF 2 VDD_REF SBLINK_CLKP_R
60 VDDHTT SRCCLKT6 16 3 4 SBLINK_CLKP (12)
17 SBLINK_CLKN_R RP401 1 2 33X2
C201 C191 SRCCLKC6 NBSRC_CLKP_R SBLINK_CLKN (12)
53 GND_CPU ATIGCLKT0 41 1 2 NBSRC_CLKP (12)
1U *0.1U 15 40 NBSRC_CLKN_R RP404 3 4 33X2
GND_SRC1 ATIGCLKC0 NBSRC_CLKN (12)
22 GND_SRC2 ATIGCLKT1 37
29 GND_SRC3 ATIGCLKC1 36
45 GND_SRC4 ATIGCLKT2 35
C
8 GND_48 ATIGCLKC2 34 C
C522 33P 38 30
CLK_VDD GND_ATIG ATIGCLKT3
1 GND_REF ATIGCLKC3 31
2
58 18 SBSRC_CLKP_R 3 4
Y402 R535 GNDHTT SRCCLKT5 SBSRC_CLKN_R RP402 33X2 CLK_PCIE_WLAN (24)
SRCCLKC5 19 1 2 CLK_PCIE_WLAN# (24)
R87 14.318MHZ *1M CLK_XIN 3 20 GPP_CLK0P_R 3 4
XIN SRCCLKT4 GPP_CLK0N_R RP403 33X2 CLK_PCIE_LAN (22)
21 1 2
1
10K C525 33P CLK_XOUT SRCCLKC4 GPP_CLK1P_R CLK_PCIE_LAN# (22)
4 XOUT SRCCLKT3 24 3 4 SBSRCCLKP (14)
25 GPP_CLK1N_R RP405 1 2 33X2
SRCCLKC3 GPP_CLK2P_R SBSRCCLKN (14)
Parallel Resonance Crystal SRCCLKT2 26
27 GPP_CLK2N_R RP406
3
1
4
2 33X2 CLK_PCIE_TV (24)
SRCCLKC2 CLK_PCIE_TV# (24)
11 RESET_IN# SRCCLKT0 47
61 NC SRCCLKC0 46
SRCCLKT1 43
SRCCLKC1 42
SRCCLKT7 12
SRCCLKC7 13
9 57 CLKREQ_WLAN#
(8,15) SCLK0 SMBCLK CLKREQA# CLKREQ_WLAN# (24)
10 32 CLKREQ_LAN#
(8,15) SDATA0 SMBDAT CLKREQB# CLKREQ_LAN# (22)
R572
R571
R567
R567
R565
R560
R560
R558
R557
R556
R566
R564
R555
R550
R550
33 CLKREQ_TV#
CLKREQC# CLKREQ_TV# (24)
48 IREF 48MHz_1 7
Ioh = 5 * Iref 6 CLK_48M_2_R R545 33
48MHz_0 USBCLK (15)
(2.32mA)
R559
Voh = 0.71V @ 60 ohm 475/F 63
FS1/REF1
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
49.9/F
64 C527
FS0/REF0 10P
FS2/REF2 62
B
HTTCLK0 59 B
ICS951462
CLK_VDD
CLKREQA# CONTROL SRC5,6,7
CLKREQB# CONTROL SRC2,3,4 ATIG3
CLKREQC# CONTROL SRC0,1 ATIG0,1,2
R78 R537 R83
10K 10K 10K
R79 *0
R536 *0
R80 *0
EXT CLK FREQUENCY SELECT TABLE(MHZ)
SB_OSCIN_R R77 33
SB_OSCIN (15)
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT
[2:1] NB_OSCIN_R R82 33
HTREFCLK_R R541 33 NB_OSC (12)
HTREFCLK (12)
0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved
0 0 1 X 100.00 X/3 X/6 48.00 Reserved C526
10P R84
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved 49.9/F
A A
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal ATHLON64 operation Quanta Computer Inc.
Check AMD clock PROJECT : GT1
Size Document Number Rev
A
Clock Generator
Date: Thursday, April 09, 2009 Sheet 3 of 36
5 4 3 2 1
5 4 3 2 1
4
CPU HyperTransport Interface
D
VDDLDTRUNCPU is connected to the VDD_LDT_RUN power D
supply through the package or on the die. It is only connected
on the board to decoupling near the CPU package.
VLDT_RUN U401A
C406
AJ4 VLDT_06 VLDT_08 H6
AJ3 VLDT_05 VLDT_07 H5
AJ2 VLDT_02 VLDT_04 H2
AJ1 VLDT_01 VLDT_03 H1
4.7U_0603
(10) HT_CADIN15_P U6 L0_CADIN_H15 L0_CADOUT_H15 Y5 HT_CADOUT15_P (10)
(10) HT_CADIN15_N V6 L0_CADIN_L15 L0_CADOUT_L15 Y4 HT_CADOUT15_N (10)
(10) HT_CADIN14_P T4 L0_CADIN_H14 L0_CADOUT_H14 AB6 HT_CADOUT14_P (10)
(10) HT_CADIN14_N T5 L0_CADIN_L14 L0_CADOUT_L14 AA6 HT_CADOUT14_N (10)
(10) HT_CADIN13_P R6 L0_CADIN_H13 L0_CADOUT_H13 AB5 HT_CADOUT13_P (10)
(10) HT_CADIN13_N T6 L0_CADIN_L13 L0_CADOUT_L13 AB4 HT_CADOUT13_N (10)
(10) HT_CADIN12_P P4 L0_CADIN_H12 L0_CADOUT_H12 AD6 HT_CADOUT12_P (10)
(10) HT_CADIN12_N P5 L0_CADIN_L12 L0_CADOUT_L12 AC6 HT_CADOUT12_N (10)
(10) HT_CADIN11_P M4 L0_CADIN_H11 L0_CADOUT_H11 AF6 HT_CADOUT11_P (10)
(10) HT_CADIN11_N M5 L0_CADIN_L11 L0_CADOUT_L11 AE6 HT_CADOUT11_N (10)
(10) HT_CADIN10_P L6 L0_CADIN_H10 L0_CADOUT_H10 AF5 HT_CADOUT10_P (10)
(10) HT_CADIN10_N M6 L0_CADIN_L10 L0_CADOUT_L10 AF4 HT_CADOUT10_N (10)
(10) HT_CADIN9_P K4 L0_CADIN_H9 L0_CADOUT_H9 AH6 HT_CADOUT9_P (10)
(10) HT_CADIN9_N K5 L0_CADIN_L9 L0_CADOUT_L9 AG6 HT_CADOUT9_N (10)
(10) HT_CADIN8_P J6 L0_CADIN_H8 L0_CADOUT_H8 AH5 HT_CADOUT8_P (10)
C (10) HT_CADIN8_N K6 L0_CADIN_L8 L0_CADOUT_L8 AH4 HT_CADOUT8_N (10) C
HT LINK
(10) HT_CADIN7_P U3 L0_CADIN_H7 L0_CADOUT_H7 Y1 HT_CADOUT7_P (10)
(10) HT_CADIN7_N U2 L0_CADIN_L7 L0_CADOUT_L7 W1 HT_CADOUT7_N (10)
(10) HT_CADIN6_P R1 L0_CADIN_H6 L0_CADOUT_H6 AA2 HT_CADOUT6_P (10)
(10) HT_CADIN6_N T1 L0_CADIN_L6 L0_CADOUT_L6 AA3 HT_CADOUT6_N (10)
(10) HT_CADIN5_P R3 L0_CADIN_H5 L0_CADOUT_H5 AB1 HT_CADOUT5_P (10)
(10) HT_CADIN5_N R2 L0_CADIN_L5 L0_CADOUT_L5 AA1 HT_CADOUT5_N (10)
(10) HT_CADIN4_P N1 L0_CADIN_H4 L0_CADOUT_H4 AC2 HT_CADOUT4_P (10)
(10) HT_CADIN4_N P1 L0_CADIN_L4 L0_CADOUT_L4 AC3 HT_CADOUT4_N (10)
(10) HT_CADIN3_P L1 L0_CADIN_H3 L0_CADOUT_H3 AE2 HT_CADOUT3_P (10)
(10) HT_CADIN3_N M1 L0_CADIN_L3 L0_CADOUT_L3 AE3 HT_CADOUT3_N (10)
(10) HT_CADIN2_P L3 L0_CADIN_H2 L0_CADOUT_H2 AF1 HT_CADOUT2_P (10)
(10) HT_CADIN2_N L2 L0_CADIN_L2 L0_CADOUT_L2 AE1 HT_CADOUT2_N (10)
(10) HT_CADIN1_P J1 L0_CADIN_H1 L0_CADOUT_H1 AG2 HT_CADOUT1_P (10)
(10) HT_CADIN1_N K1 L0_CADIN_L1 L0_CADOUT_L1 AG3 HT_CADOUT1_N (10)
(10) HT_CADIN0_P J3 L0_CADIN_H0 L0_CADOUT_H0 AH1 HT_CADOUT0_P (10)
(10) HT_CADIN0_N J2 L0_CADIN_L0 L0_CADOUT_L0 AG1 HT_CADOUT0_N (10)
(10) HT_CLKIN1_P N6 L0_CLKIN_H1 L0_CLKOUT_H1 AD5 HT_CLKOUT1_P (10)
(10) HT_CLKIN1_N P6 L0_CLKIN_L1 L0_CLKOUT_L1 AD4 HT_CLKOUT1_N (10)
VLDT_RUN N3 AD1
(10) HT_CLKIN0_P L0_CLKIN_H0 L0_CLKOUT_H0 HT_CLKOUT0_P (10)
(10) HT_CLKIN0_N N2 L0_CLKIN_L0 L0_CLKOUT_L0 AC1 HT_CLKOUT0_N (10)
R10 49.9/F HT_CTLIN1_P V4 Y6 HT_CPU_CTLOUT1_P
L0_CTLIN_H1 L0_CTLOUT_H1 T9
R11 49.9/F HT_CTLIN1_N V5 W6 HT_CPU_CTLOUT1_N
L0_CTLIN_L1 L0_CTLOUT_L1 T8
(10) HT_CTLIN0_P U1 L0_CTLIN_H0 L0_CTLOUT_H0 W2 HT_CTLOUT0_P (10)
(10) HT_CTLIN0_N V1 L0_CTLIN_L0 L0_CTLOUT_L0 W3 HT_CTLOUT0_N (10)
B B
Athlon 64 M2
Processor Socket
VLDT_RUN
1
1
C404 C405
C410 C407 C408 C411
4.7U_0603 4.7U_0603 0.22U 0.22U 180P 180P
2
2
A A
Quanta Computer Inc.
PROJECT : GT1
Size Document Number Rev
A
AMD M2+ HT I/F
Date: Thursday, April 09, 2009 Sheet 4 of 36
5 4 3 2 1
5 4 3 2 1
Processor DDR2 Memory Interface 1.8VSUS
(8) M_B_DQ[0..63]
M_B_DQ63 AH13
U401C
AE14 M_A_DQ63
M_A_DQ[0..63] (8)
5
M_B_DQ62 MB_DATA63 MA_DATA63 M_A_DQ62 R22
AL13 MB_DATA62 MA_DATA62 AG14
M_B_DQ61 AL15 AG16 M_A_DQ61 2K/F
M_B_DQ60 MB_DATA61 MA_DATA61 M_A_DQ60
AJ15 MB_DATA60 MA_DATA60 AD17
M_B_DQ59 AF13 AD13 M_A_DQ59 CPU_M_VREF
M_B_DQ58 MB_DATA59 MA_DATA59 M_A_DQ58
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