Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_EL8
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VCC_CORE EL8 Block Diagram 01
GMCH_CORE
Intel
CLOCK GENERATOR
Yorkfield/Wolfdale
CK505
A
VCC1.1 Q9000/E8000 CV193
A
VCC1.2 LGA775 Page 2
Page 3,4
VCC1.5
1.5VSUS FSB(800/1067/1333HZ)
CH A: DDRIII-UDIMM0/1
800/1067 MHZ DDR III
CH B: DDRIII-UDIMM0/1
VCC3 Page 14,15,16,17
3V_STBY NB
SATA 4 Eaglelake
SATA - HDD(2.5)
VCC5 Page 22
G45/P43 PCI-E 2.0 16X MXM CONNECTOR
1254 pin
5V_STBY SATA 1
SATA - HDD(3.5) Page 5,7,8,9
Page 22 Page 18
+12V
SATA 2 LCD PANEL
LVDS
SATA - ODD
Page 22
DMI
23" Full HD
SATA 3
B
eSATA LVDS Transmitter
B
Page 22 SDVO
CH7308B Page 19
USB-10 USB 2.0
WLAN
Page 25
USB-1
Camera PCI-Express 1X
Page 19
PCIE-2 PCIE-3 PCIE-1 PCIE-4
USB-2
BT KB/Mouse Bluetooth SB
Page 27 Page 26
USB-6,7 ICH10 MINI CARD-1 MINI CARD-2 LAN Card Reader
8,9 676 pin WLAN TV card RTL8111DL JMB385
Azalia Page 25 Page 25 Page 26 Page 27
USB*4(Rear)
Page 27
USB-11
TV
Page 25
WLAN antenna TV antenna RJ45 Media Slot
USB-3,5
C USB*2(Side) C
Page 26
Page 10,11,12,13
USB-0
Touch Screen Daughter
MXM module
Page 27
314 pin
Board
LPC 32.768KHz
B-CAS board
10 pin
ITE8512
Card Reader
20 pin
HP Page 26
Page 30
AUDIO CODEC HP/MIC
ALC888S-VC2 Light SW
MIC IN 10 pin
Page 29
Page 30
Power button
D
LED TBD
D
INT SPK
Page 29
IR FLASH
FAN CIR
Blaster ROM
Page 3 Page 26 Page 28 Page 28
DMIC IN
Page 30
PROJECT : EL8
LINE IN 5.1 Channel Quanta Computer Inc.
Size Document Number Rev
Block Diagram 1A
Date: Monday, March 09, 2009 Sheet 1 of 34
1 2 3 4 5 6 7 8
5 4 3 2 1
Clock Generator
02
VCC1.2_VDD
PBY160808T-301Y-N_6 L1 VCC1.2
C1 C2 C3 C4 C5 C6 C7 C8
*10u/10V_6 10u/10V_6 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4
U1
VCC3
D 1 54 CLK_CPU_BCLK_R RP1 1 2 0X2 D
PCI0/CR#_A CPUT0 CLK_CPU_BCLK 3
3 53 CLK_CPU_BCLK#_R 3 4 To CPU
PCI1/CR#_B CPUC0 CLK_CPU_BCLK# 3
2.2K/J_4 R1 PM_STPPCI# PCLK_DEBUG R2 33/J_4 PCLK_DEBUG_R 4
VCC3 24 PCLK_DEBUG *PCI2/SR_ENABLE
PCLK_EC R3 33/J_4 PCLK_EC_R 5 51 CLK_MCH_BCLK_R RP2 1 2 0X2
26 PCLK_EC **PCI3/SATA_SEL CPUT1 CLK_MCH_BCLK 5
2.2K/J_4 R4 PM_STPCPU# PCLK_ICH R5 33/J_4 PCLK_ICH_R 6 50 CLK_MCH_BCLK#_R 3 4 To NB
11 PCLK_ICH PCI4/SRC5_EN CPUC1 CLK_MCH_BCLK# 5
PCIF5_ITPEN R6 33/J_4 PCIF5_ITPEN_R 7
PCI_F5/ITP_EN XDP_DCLKOUT_DP_R RP3
47 1 2 0X2 XDP_DCLKOUT_DP 3
R7 SRCT8/CPU_ITPT XDP_DCLKOUT_DN_R
SRCC8/CPU_ITPC
46 3 4 XDP_DCLKOUT_DN 3 To CPU
1K/J_4 SEL_SRC1 48
SEL_SRC1_25_24.576**
10 PM_STPCPU# PM_STPCPU# 37 13 DREFCLK_R RP4 3 4 IV@0X2
CPU_STOP#/SRCC5 DOT96T/SRCT0 DREFCLK 6
SEL_SRC1 PM_STPPCI# DREFCLK#_R To NB
Pin17-18. SRC1 enabled 10 PM_STPPCI#
CK_PWRGD
38
56
PCI_STOP#/SRCT5 DOT96C/SRCC0
14 1 2 DREFCLK# 6
10 CK_PWRGD CKPWRGD/PD#
17 DREFSSCLK_R RP5 3 4 IV@0X2
SRCT1/25MHz0 DREFSSCLK 6
R8 18 DREFSSCLK#_R 1 2 To NB
SRCC1/25MHz1/24.576MHz DREFSSCLK# 6
1K/J_4 CGCLK_SMB 64
CGDAT_SMB SCL CLK_PCIE_SATA_R RP6
63 21 3 4 0X2 CLK_PCIE_SATA 12
SDA SRCT2/SATAT CLK_PCIE_SATA#_R
SRCC2/SATAC
22 1 2 CLK_PCIE_SATA# 12 To SB
CG_XIN 60
CG_XOUT XTAL_IN MXM_PEGCLK_R RP7
59 24 3 4 EV@0X2 MXM_PEGCLK 18
XTAL_OUT SRCT3/CR#_C MXM_PEGCLK#_R
CK505 SRCC3/CR#_D
25 1 2 MXM_PEGCLK# 18 To MXM
VCC3 L2 PBY160808T-301Y-N_6 C9 0.1u/10V_4 27 CLK_PCIE_EXP_R RP8 3 4 0X2
SRCT4 CLK_PCIE_EXP 6
12 28 CLK_PCIE_EXP#_R 1 2 To NB
VDDIO SRCC4 CLK_PCIE_EXP# 6
20
C10 VDDPLL3IO CLK_PCIE_ICH_R RP9
26 41 1 2 0X2 CLK_PCIE_ICH 11
C11 0.1u/10V_4 VDDSRCIO SRCT6 CLK_PCIE_ICH#_R
36
VDDSRCIO SRCC6
40 3 4 CLK_PCIE_ICH# 11 To SB
10u/10V_6 45
C12 10u/10V_6 VCC1.2_VDD VDDSRCIO CLK_PCIE_LAN_R RP10
49 44 1 2 0X2 CLK_PCIE_LAN 22
VDDCPUIO SRCT7/CR#_F CLK_PCIE_LAN#_R
SRCC7/CR#_E
43 3 4 CLK_PCIE_LAN# 22 To LAN
VDD_CK_VDD_PLL3 16 30 CLK_PCIE_MINI_R RP11 3 4 0X2
VDDPLL3 SRCT9 CLK_PCIE_MINI 24
C13 0.1u/10V_4 VDD_CK_VDD_PCI 2 31 CLK_PCIE_MINI#_R 1 2 To WLAN
VDDPCI SRCC9 CLK_PCIE_MINI# 24
VDD_CK_VDD_48 9
C14 0.1u/10V_4 VDD_CK_VDD_REF VDD48 CLK_PCIE_MINI2_R RP12
61 34 3 4 0X2 CLK_PCIE_MINI2 24
VDD_CK_VDD_CPU VDDREF SRCT10 CLK_PCIE_MINI2#_R
C
55
VDDCPU SRCC10
35 1 2 CLK_PCIE_MINI2# 24 To TV C
VDD_CK_VDD_SRC 39
C15 0.1u/10V_4 VDDSRC CLK_PCIE_JMB385_R RP13
33 1 2 0X2 CLK_PCIE_JMB385 25
SRCT11/CR#_H CLK_PCIE_JMB385#_R
SRCC11/CR#_G
32 3 4 CLK_PCIE_JMB385# 25 To Card Reader
C16 0.1u/10V_4
42
C17 0.1u/10V_4 GNDSRC
52
GNDCPU FSA 33/J_4 R9
23 10 CLKUSB_48 11
GNDSRC USB48/FS_A 1K/J_4 R10 CLK_BSEL0
19
GND FSB 1K/J_4 R11 CLK_BSEL1
15 57
GND FS_B/TESTMODE
11
GND48 FSC 1K/J_4 R12 CLK_BSEL2
8 62
GNDPCI REF/FS_C/TESTSEL 22/J_4 R13
29 14M_ICH 10
GNDSRC IV@*22/J_4 R151
58 14M_CH7308B 19
GNDREF
CV193 *Internal 100K Pull High
Strap Configuration **Internal 100K Pull Low
R14 10K/J_4 PCLK_DEBUG_R
VCC3 Internal 33 ohm resistor enabled
R15 *10K/J_4
C18 27p/50V_4 CG_XIN
R16 *10K/J_4 PCLK_EC_R
VCC3 SATA output from PLL2
2
Y1
CL=20p
R17 10K/J_4 14.318MHZ
1
C19 27p/50V_4 CG_XOUT
R18 *10K/J_4 PCLK_ICH_R
VCC3 CPUSTP#/PCISTP enabled
B R19 10K/J_4 B
R20 10K/J_4 PCIF5_ITPEN
VCC3 ITPCLK enabled
R21 *10K/J_4
Clock Gen I2C
FREQ. SEL TABLE PCIF5_ITPEN C491 *10p
PCLK_EC C20 *10p
BSEL Frequency Select Table R22 0/J_4 CLK_BSEL0R23 0/J_4 MCH_BSEL0 VCC3
3 CPU_BSEL0 MCH_BSEL0 6
FSC FSB FSA Frequency CLKUSB_48 C21 *10p
R24 *0/J_4
0 0 0 266Mhz Q1 R26 14M_ICH C22 *10p
VCC1.2 R25 470/J_4
2
RHU002N06 10K/J_4
0 0 1 133Mhz PCLK_ICH C23 *10p
3 1 CGDAT_SMB
10,14 SDATA
0 1 1 166Mhz PCLK_DEBUG C24 *22p
R27 0/J_4 CLK_BSEL1 R28 0/J_4 MCH_BSEL1
3 CPU_BSEL1 MCH_BSEL1 6
VCC3
0 1 0 200Mhz 14M_CH7308B C492 *10p
R29 *0/J_4
A A
1 0 0 333Mhz
VCC1.2 R30 470/J_4 Q2 R31
2
1 0 1 100Mhz RHU002N06 10K/J_4
3 1 CGCLK_SMB
10,14 SCLK
1 1 0 400Mhz R32 0/J_4 CLK_BSEL2 R33 0/J_4 MCH_BSEL2
3 CPU_BSEL2 MCH_BSEL2 6
1 1 1 Reserved R34 *0/J_4 PROJECT : EL8
VCC1.2 R35 470/J_4 Quanta Computer Inc.
Size Document Number Rev
CLK. GEN./ CK505 1A
Date: Monday, March 09, 2009 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1
U2A U2B
5 H_A#[3..16]
H_A#3
H_A#4
H_A#5
L5
P6
M5
H_A3
H_A4
H_D0
H_D1
B4
C5
A4
H_D#0
H_D#1
H_D#2
H_D#[0..15] 5
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