Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_EL3_DAOEL3MB6E0
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5 4 3 2 1
PCB STACK UP BENQ(EL3) LCDPC Block Diagram
LAYER 1 : TOP
LAYER 2 : GND
LAYER 3 : IN1 VID[0:5] CPU VCORE
D
LAYER 4 : IN2
LAYER 5 : VCC
DDRII CHA AMD MAX8799 D
LAYER 6 : BOT 512M//1GB/2GB/4GB VCORE:+0.375V ~ +1.5V 30A
VLDT:+1.2V 1A
VCCA:+2.5V 0.25A +/- CPU_CLK
812-PIN BGA
+/- HCLK Clock Gengerator
ICS951462
HT-LINK
18.5" panel LVDS
AUO/CMO RS690E
HOST PCI-E
C
LVDS, DMI, DDR CLK
USB
MINI CARD WLAN C
PCI-E POWER
PCI-E
GND Module
10/100 Ethernet 21mmX21mm FCBGA 465PIN EM106
RJ-45
RTL8102EL A_LINK SATA
HDD
Card Reader SB600 IDE SSD module/ZIF
4 in 1 JMB385E RTC, AC97, SATA, IDE, LPC, CPU
B
PCI-E, USB, DMI, PCI
SMB, GPIO, CLK
USB WebCam Conn.
Camera B
Module
HDA CODEC
SPK ALC269 2WX2 HD_AUDIO 23mmX23mm FCBGA 549PIN
USB USB PORT X4
USB LPC BUS
Headohone Out USB X2
TPM EC SPI
Int. Mic ITE8512
A Flash A
Quanta Computer Inc.
PROJECT : BENQ
Size Document Number Rev
1A
Block Diagram
Date: Tuesday, January 06, 2009 Sheet 1 of 35
5 4 3 2 1
5 4 3 2 1
5VPCU
1A 5VSUS
SW
D
SUSON Control By EC D
SW VCC5
MAINON
PU6
VCC1.2SUS VCC1.2
SW
SUSON
5VPCU(3A)
SW VCC1.5
VIN Always ON
3VPCU(3A) MAINON
PWM 3VPCU
SW 3VSUS
SUSON Control By EC
C C
SW RVCC3
RVCC_ON Control By EC
SW VCC3
MAINON
LDO CPU_VDDA(2.5V)
MAINON
VIN 1.8VSUS
PWM SW VCC1.8
Power On Sequence
B
MAINON B
ACIN
5VPCU/3VPCU
SUSON VTERM NBSWON#
(0.9V) PWRBTN#
RVCC_ON
RSMRST#
VIN 12A SUSB#,SUSC#
PWM +VCORE SUSON
VRON MAINON
VSUS,VCC
DCIN ALWAYS ON S4 OFF S3 OFF VR_ON
VCORE_CPU
NB_PWRGD
A A
PWROK
PCIRST# SB600
Quanta Computer Inc.
PROJECT : EL3
Size Document Number Rev
1A
Block Diagram
Date: Tuesday, January 06, 2009 Sheet 2 of 35
5 4 3 2 1
5 4 3 2 1
VCC3
CLK_VDD VCC3
L2 BK1608HS600_6
L1 BK1608HS600_6 CLK_VDDA
C1
C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
22U/6.3V_8 0.1U_4 0.1U_4 0.1U_4 *0.1U_4 0.1U_4 0.1U_4 0.1U_4 0.1U_4 0.1U_4 10U_0805
D D
Put Decoupling Caps close to Clock Gen. power pin
VCC3
CLK_VDD
L3 BK1608HS600_6 CLK_VDD_USB U1
C12 54 50 CLK_VDDA
C13 VDDCPU VDDA R1 261/F_4
14 VDD_SRC1 GNDA 49
10u/6.3V_6 0.1U_4 23 VDD_SRC2 CPUCLK_EXT_R R2 47.5/F_4
28 VDD_SRC3 CPUCLK8T0 56 CPUCLKP 6
44 55 CPUCLK#_EXT_R R3 47.5/F_4
VCC3 5
VDD_SRC4 CPUCLK8C0
52
CPUCLKN 6 200MHZ
VDD_48 CPUCLK8T1
39 VDD_ATIG CPUCLK8C1 51
L4 BK1608HS600_6 CLK_VDD_REF 2 VDD_REF SBLINK_CLKP_R
60 VDDHTT SRCCLKT6 16 3 4 SBLINK_CLKP 10
C14 17 SBLINK_CLKN_R RP1 1 2 33X2
C15 SRCCLKC6 NBSRC_CLKP_R SBLINK_CLKN 10
10u/6.3V_6 0.1U_4
53
15
GND_CPU ATIGCLKT0 41
40 NBSRC_CLKN_R RP2
1
3
2
4 33X2
NBSRC_CLKP 10 100MHZ
GND_SRC1 ATIGCLKC0 NBSRC_CLKN 10
22 GND_SRC2 ATIGCLKT1 37
29 GND_SRC3 ATIGCLKC1 36
45 GND_SRC4 ATIGCLKT2 35
C
8 GND_48 ATIGCLKC2 34 C
C16 33P_4 38 30
CLK_VDD GND_ATIG ATIGCLKT3
1 GND_REF ATIGCLKC3 31
2
58 18 SBSRC_CLKP_R 3 4
Y1 R4 GNDHTT SRCCLKT5 SBSRC_CLKN_R RP3 33X2 CLK_PCIE_WLAN 21
SRCCLKC5 19 1 2 CLK_PCIE_WLAN# 21
R5 14.318MHZ *1M_4 CLK_XIN 3 20 GPP_CLK0P_R 3 4
XIN SRCCLKT4 GPP_CLK0N_R RP4 33X2 CLK_PCIE_LAN 25
21 1 2 100MHZ
1
10K_4 C17 33P_4 CLK_XOUT SRCCLKC4 GPP_CLK1P_R CLK_PCIE_LAN# 25
4 XOUT SRCCLKT3 24 3 4 SBSRCCLKP 14
25 GPP_CLK1N_R RP5 1 2 33X2
SRCCLKC3 GPP_CLK2P_R SBSRCCLKN 14
Parallel Resonance Crystal SRCCLKT2 26
27 GPP_CLK2N_R RP6
3
1
4
2 33X2 PE0CLK+ 27
SRCCLKC2 PE0CLK- 27
11 RESET_IN# SRCCLKT0 47
61 NC SRCCLKC0 46
SRCCLKT1 43
SRCCLKC1 42
SRCCLKT7 12
SRCCLKC7 13
13,15 SCLK0 9 SMBCLK CLKREQA# 57
13,15 SDATA0 10 SMBDAT CLKREQB# 32
R9
R17
R10
R10
R11
R12
R12
R18
R19
R13
R14
R20
R21
R15
R15
CLKREQC# 33
C18 C19 48 7
*0.1U_4 *0.1U_4 IREF 48MHz_1 CLK_48M_2_R R8 33//F_4
Ioh = 5 * Iref 48MHz_0 6 USBCLK 15
(2.32mA) R16
Voh = 0.71V @ 60 ohm 475/F_4 63
48MHZ
FS1/REF1
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
FS0/REF0 64
FS2/REF2 62
B
HTTCLK0 59 B
ICS951462
CLK_VDD
CLKREQA# CONTROL SRC5,6,7
CLKREQB# CONTROL SRC2,3,4 ATIG3
CLKREQC# CONTROL SRC0,1 ATIG0,1,2
R22 R23 R24
10K_4 10K_4 10K_4
R25 *0_4
R26 *0_4
R27 *0_4
EXT CLK FREQUENCY SELECT TABLE(MHZ)
SB_OSCIN_R R28 33_4
SB_OSCIN 15
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT 14MHZ
[2:1] NB_OSCIN_R R29 33_4
HTREFCLK_R R30 33_4 NB_OSC 10
HTREFCLK 10
0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved 66MHZ
0 0 1 X 100.00 X/3 X/6 48.00 Reserved
R31
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved 49.9/F-4
A A
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal operation Quanta Computer Inc.
PROJECT : BenQ
Size Document Number Rev
1A
Clock Generator
Date: Tuesday, January 06, 2009 Sheet 3 of 35
5 4 3 2 1
5 4 3 2 1
LAYOUT NOTE: VLDT must be routed as
a pour or a trace at least 100 mils wide.
VLDT may be routed from the source to
either ALx balls or Fx balls. Choose
whichever makes routing simpler.
D VCC1.2 VLDT_RUN D
L5
VLDT_RUN *FBJ3216HS800_1206
U2A L6
AL4 VLDT_B4 VLDT_A4 F4
AL3 F3 *FBJ3216HS800_1206
VLDT_B3 VLDT_A3
AL2 VLDT_B2 VLDT_A2 F2
AL1 F1 C20
VLDT_B1 VLDT_A1 4.7U_6
8 HT_CADIN15_P Y6 L0_CADIN_H15 L0_CADOUT_H15 Y9 HT_CADOUT15_P 8
8 HT_CADIN15_N Y5 L0_CADIN_L15 L0_CADOUT_L15 Y8
HT_CADOUT15_N 8
8 HT_CADIN14_P W7 L0_CADIN_H14 L0_CADOUT_H14 AB6
HT_CADOUT14_P 8
8 HT_CADIN14_N W6 L0_CADIN_L14 L0_CADOUT_L14 AB5
HT_CADOUT14_N 8
8 HT_CADIN13_P U6 L0_CADIN_H13 L0_CADOUT_H13 AC7
HT_CADOUT13_P 8
8 HT_CADIN13_N U5 L0_CADIN_L13 L0_CADOUT_L13 AC6 HT_CADOUT13_N 8
R7 AE6 C21 C22 C23 C24 C25 C26
8 HT_CADIN12_P L0_CADIN_H12 L0_CADOUT_H12 HT_CADOUT12_P 8
R6 AE5 4.7u/6.3V_6 4.7u/6.3V_6 .22u/6.3V_4 .22u/6.3V_4 180P_NPO_4 180P_NPO_4
8 HT_CADIN12_N L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUT12_N 8
8 HT_CADIN11_P M8 L0_CADIN_H11 L0_CADOUT_H11 AE9
HT_CADOUT11_P 8
8 HT_CADIN11_N M7 L0_CADIN_L11 L0_CADOUT_L11 AE8
HT_CADOUT11_N 8
C 8 HT_CADIN10_P L6 L0_CADIN_H10 L0_CADOUT_H10 AH3 HT_CADOUT10_P 8 C
8 HT_CADIN10_N L5 L0_CADIN_L10 L0_CADOUT_L10 AH4
HT_CADOUT10_N 8
8 HT_CADIN9_P J6 L0_CADIN_H9 L0_CADOUT_H9 AK3
HT_CADOUT9_P 8
8 HT_CADIN9_N J5 L0_CADIN_L9 L0_CADOUT_L9 AK4
HT_CADOUT9_N 8
8 HT_CADIN8_P H4 L0_CADIN_H8 L0_CADOUT_H8 AK1
HT_CADOUT8_P 8
8 HT_CADIN8_N H3 L0_CADIN_L8 L0_CADOUT_L8 AK2 HT_CADOUT8_N 8
8 HT_CADIN7_P T3 L0_CADIN_H7 L0_CADOUT_H7 Y1
HT_CADOUT7_P 8
8 HT_CADIN7_N T4 L0_CADIN_L7 L0_CADOUT_L7 Y2
HT_CADOUT7_N 8
T2 Y4
8
8
HT_CADIN6_P
HT_CADIN6_N T1
L0_CADIN_H6
L0_CADIN_L6
L0_CADOUT_H6
L0_CADOUT_L6 Y3
HT_CADOUT6_P 8
HT_CADOUT6_N 8 VLDT_RUN
HT LINK
8 HT_CADIN5_P P3 L0_CADIN_H5 L0_CADOUT_H5 AB1 HT_CADOUT5_P 8
8 HT_CADIN5_N P4 L0_CADIN_L5 L0_CADOUT_L5 AB2
HT_CADOUT5_N 8
8 HT_CADIN4_P P2 L0_CADIN_H4 L0_CADOUT_H4 AB4
HT_CADOUT4_P 8 PQ35 AO4468
P1 AB3 5VPCU VLDT_RUN 15VPCU
8 HT_CADIN4_N L0_CADIN_L4 L0_CADOUT_L4 HT_CADOUT4_N 8
8 HT_CADIN3_P M2 L0_CADIN_H3 L0_CADOUT_H3 AD4 VCC1.2 8 1 VLDT_RUN
HT_CADOUT3_P 8
8 HT_CADIN3_N M1 L0_CADIN_L3 L0_CADOUT_L3 AD3 HT_CADOUT3_N 8 7 2
8 HT_CADIN2_P K3 L0_CADIN_H2 L0_CADOUT_H2 AF1 6 3
HT_CADOUT2_P 8
8 HT_CADIN2_N K4 L0_CADIN_L2 L0_CADOUT_L2 AF2 5
HT_CADOUT2_N 8 PR123 PR124 PR125
8 HT_CADIN1_P K2 L0_CADIN_H1 L0_CADOUT_H1 AF4
HT_CADOUT1_P 8 100K_6 22R 1M
8 HT_CADIN1_N K1 AF3
4
L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUT1_N 8
8 HT_CADIN0_P H2 L0_CADIN_H0 L0_CADOUT_H0 AH1 HT_CADOUT0_P 8
8 HT_CADIN0_N H1 L0_CADIN_L0 L0_CADOUT_L0 AH2
HT_CADOUT0_N 8 VLDTONG VLDTD
VLDTD 34
8 HT_CLKIN1_P P6 L0_CLKIN_H1 L0_CLKOUT_H1 AF6
HT_CLKOUT1_P 8
3
3
B 8 HT_CLKIN1_N P5 L0_CLKIN_L1 L0_CLKOUT_L1 AF5 B
HT_CLKOUT1_N 8
3
8 HT_CLKIN0_P M3 L0_CLKIN_H0 L0_CLKOUT_H0 AD1
VLDT_RUN HT_CLKOUT0_P 8 PR126
8 HT_CLKIN0_N M4 AD2 2 1 1
L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUT0_N 8 26 VLDT_ON
*1K PC128
R32 51_4 HT_CTLIN1_P P8 AB8 HT_CPU_CTLOUT1_P PQ36 PQ37 PQ38 *2200p/50V/X7R
L0_CTLIN_H1 L0_CTLOUT_H1 T3
R33 51_4 HT_CTLIN1_N P9 AB9 HT_CPU_CTLOUT1_N DDTC144EUA-7-F ME2N7002E ME2N7002E
T4
1
L0_CTLIN_L1 L0_CTLOUT_L1
2
2
8 HT_CTLIN0_P V2 L0_CTLIN_H0 L0_CTLOUT_H0 V4
HT_CTLOUT0_P 8
8 HT_CTLIN0_N V1 L0_CTLIN_L0 L0_CTLOUT_L0 V3
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