Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_TA7
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5 4 3 2 1
14.318MHz
TA7 BLOCK DIAGRAM
Cable Docking CON. CLOCK GEN
ICS9LPRS365
Merom / Crestline / ICH8-M
RJ45 64pins
IEEE 1394
MAX1993 VGACORE
Merom PG 2 (1.1V/1.2V) PG 49
CRT
D D
Headphone (478 Micro-FCPGA)
USB 2.0
2.5V
CPU THERMAL PG 48
Power Jack SENSOR
PG 38 PG 3
PG 3,4 SYSTEM POWER(3/5V)
PG 48
VIDEO RAM *2
FSB
DDRIII PG 23
CPU CORE POWER ISL6262A
667/800 MHz PG 47
64bit/256MB
+1.5V
DDRII-SODIMM1 DDRII 533/667 MHz
Crestline ATI LCD Panel PG 46
PG12, 13
1299 uFCBGA PG 24 +1.05V/+1.25V
PCI-EXPRESS M71S
DDRII 533/667 MHz PG 45
DDRII-SODIMM2 CRT
PG 12,13 +1.8VSUS/+0.9V
PG 25
PG 44
FINGER PRINT PG 5,6,7,8,9,10,11
C C
USB8 PG 18,19,20,21,22 CHARGER MAX8724 &
PG 36 DMI LINK
SELECTER PG 41,42
32.768KHz
4X PCI-E FOR Crestline (LCD/CRT)
Bluetooth
USB6 DISCHARGE
PG 38 PG 40
33MHZ, 3.3V PCI
USB PORT X 3 USB 2.0 ICH8-M
USB0~1
USB2~3 PG 34 676 BGA PCI-E
24.576MHz
Azalia
PATA ODD PATA
AUX Battery
MDC Module 1.5 Azalia Intel 82566 MINI PCI-E Card * 2 CARDBUS / IEEE 1394
PG 33 STAC9200 USB7 CONTROLLER/CF
PG14,15,16,17
USB9 R5C843
PG 30 PG 30 PG 26 PG 32 PG 28
25MHz
Internal HDD SATA
B
PG 33 B
Amplifier SIM Card 4 IN 1 CARDBUS 1394
MAX9789A SLOT X1 CONN
CARD READER
SD/MMC, MS,XD
LPC PG 31 PG 32
32.768KHz PG 29 PG 28 PG 28
WIRE
PCI DEVICES IRQ ROUTING
TPM SIO PC87381 RJ11 JACK RJ45
IT8512
Digitizer
JACK HEADPHONE, JACK DEVICE IDSEL # REQ/GNT # PCI_INT
2ND HEADPHONE,
MIC CardBus/1394 AD25 0 A,B,C
PG 38
LQFP 128 PG 37 PG 31 PG 27
PG 35
A A
SPI FLASH
FAN Touchpad Keyboard
PG 36 PG 36 PG 36 PG 35
PROJECT : TA7
Quanta Computer Inc.
Size Document Number Rev
1A
Block Diagram
Date: Friday, March 02, 2007 Sheet 1 of 49
5 4 3 2 1
5 4 3 2 1
+CK_VDD_MAIN +3.3V
+3.3V_M L88 C775 0.1U/10V/X5R_4 L90
BLM21PG600SN1D 2 1 +3.3V_M MINI1CLK_REQ# R632 10K_4
+CK_VDD_MAIN2 BLM21PG600SN1D MINI2CLK_REQ# R650 10K_4
iAMT CLK_3GPLLREQ# R649 10K_4
C757 C758 0.1U/10V/X5R_4 iAMT SATA_CLKREQ# R622 10K_4
10U/6.3V/X5R_8 C783 C771 C779 C765 C774 C770 C767 C776
C443 4.7U/10V/X5R_8 0.1U/10V/X5R_4
0.1U/10V/X5R_4 0.1U/10V/X5R_4
0.1U/10V/X5R_4 0.1U/10V/X5R_4
0.1U/10V/X5R_4 10U/6.3V/X5R_8
4.7U/10V/X5R_8
C760 0.1U/10V/X5R_4 U37 Clock Gen
2 VDD_PCI NC 48 T159 Clock Gen I2C
C764 0.1U/10V/X5R_4 9
16
VDD_48
64 CGCLK_SMB_M iAMT +3.3V_M
D VDD_PLL3 SCLK CGDAT_SMB_M CGCLK_SMB_M 12,13 D
61 VDD_REF SDA 63 CGDAT_SMB_M 12,13
C768 0.1U/10V/X5R_4
CK505
39 VDD_SRC PCI_STOP# 38 H_STP_PCI# 16
55 37 R627 R628
VDD_CPU CPU_STOP# H_STP_CPU# 16
10K_4 10K_4
+CK_VDD_MAIN 12 54 CPU_BCLK 4 3 RP43
VDD_96_IO CPU0 CLK_CPU_BCLK 3
2
C762 0.1U/10V/X5R_4 20 53 CPU_BCLK# 2 1 0X2 Q49
VDD_PLL3_IO CPU0# CLK_CPU_BCLK# 3
26 2N7002W-7-F
VDD_SRC_IO_1 MCH_BCLK
CPU1 51 4 3 RP44 CLK_MCH_BCLK 5 16,32 ICH_SMBDATA 3 1 CGDAT_SMB_M
36 50 MCH_BCLK# 2 1 0X2
VDD_SRC_IO_2 CPU1# CLK_MCH_BCLK# 5
16 SATA_CLKREQ# 49 VDD_CPU_IO
45 47 CPU_ITP 4 3 RP45 CLK_CPU_ITP T160
32 MINI1CLK_REQ# VDD_SRC_IO_3 SRC8/ITP
46 CPU_ITP# 2 1 *0X2 CLK_CPU_ITP# T161 +3.3V_M
SRC8#/ITP#
R343 10K_4 R623 475/F_4 SATACLKREQ#_R 1 35 MCH_3GPLL# 4 3 RP49
+3.3V PCI0/CR#_A SRC10# CLK_MCH_3GPLL# 6
34 MCH_3GPLL 2 1 0X2
38 CLK_PCI_TPM SRC10 CLK_MCH_3GPLL 6
2
R636 475/F_4PCI_CLK_R5C843_R 3 Q50
32 PCLK_LPC_DEBUG PCI1/CR#_B
33 CLK_3GPLLREQ#_R R648 475/F_4 CLK_3GPLLREQ# 6 2N7002W-7-F
R346 22_4 PCLK_TPM_R SRC11/CR#_H MINI2CLK_REQ#_R R651 475/F_4 CGCLK_SMB_M
4 PCI2/TME SRC11#/CR#_G 32 MINI2CLK_REQ# 32 16,32 ICH_SMBCLK 3 1
R344 22_4
R637 22_4 PCLK_8512_R 5 30 PCIE_MINI2 2 1 RP48
35 PCI_CLK_8512 PCI3 SRC9 CLK_PCIE_MINI2 32
28 PCLK_7412
R352 12.1/F_4
SRC9# 31 PCIE_MINI2# 4 3 0X2 CLK_PCIE_MINI2# 32
R351 12.1/F_4 FCTSEL1 6 PCI4/27MHz_Select PECLK_VGA_R
SRC7/CR#_F 44 4 3 RP47 CLK_PCIE_VGA 18
R639 22_4 PCI_ICH 7 43 PECLK_VGA#_R 2 1 0X2 Discrete
PCIF5/ITP_EN SRC7#/CR#_E CLK_PCIE_VGA# 18
+3.3V R357 10K_4@EV
CG_XIN 60 41 PCIE_ICH 2 1 RP37
37 PCI_CLK_SIO XTAL_IN SRC6 CLK_PCIE_ICH 15
R355 *10K_4@IV
SRC6# 40 PCIE_ICH# 4 3 0X2 CLK_PCIE_ICH# 15
CG_XOUT 59 XTAL_OUT PCIE_MINI1
SRC4 27 4 3 RP38 CLK_PCIE_MINI1 32
PCI4/27_Select: 1=27MHz,0=SRC_100MHz FSA 10 28 PCIE_MINI1# 2 1 0X2
USB_48/FSA SRC4# CLK_PCIE_MINI1# 32
C of Pin17 & Pin18. 57 24 C
FSB/TEST/MODE SRC3/CR#_C
SRC3#/CR#_D 25
FSC 62 REF0/FSC/TESTSEL PCIE_SATA
SRC2/SATA 21 4 3 RP36 CLK_PCIE_SATA 14
8 22 PCIE_SATA# 2 1 0X2
VSS_PCI SRC2#/SATA# CLK_PCIE_SATA# 14
11 VSS_48
15 17 DREFSSCLK_R 2 1 RP46
VSS_IO SRC1/SE1/27MHz_NonSS DREF_SSCLK 6
19 VSS_PLL3 SRC1#/SE2/27MHz_SS 18 DREFSSCLK#_R 4 3 *0X2@IV DREF_SSCLK# 6
+3.3V R642 10K_4 52 UMA & Discrete setting
VSS_CPU DREFCLK_R
15 CLK_PCI_ICH 23 VSS_SRC1 SRC0/DOT96 13 4 3 RP34 MCH_DREFCLK 6 CLK Discrete / UMA
R640 *10K_4@NC 29 14 DREFCLK#_R 2 1 *0X2@IV
42
VSS_SRC2 SRC0#/DOT96# MCH_DREFCLK# 6 ---------------------
VSS_SRC3 RP47 0 NC
PCIF5/ITP_EN: PU be used, the CK505 will 58 VSS_REF CKPWRGD/PWRDWN# 56
be configured to use Pin46/47 to CPU ITP RP46 NC 0
ICS9LPRS365BGLFT 4 3 RP35
clock.If PD be detect at powe-on,the CK505 2 1 0X2
CLK_VGA_27M_NSS 19 RP34 NC 0
CLK_VGA_27M_SS 19
will setting Pin 46/47 to SRC8(Default is RP35 0 NC
setting to SRC8) UMA & Discrete Dis/Enable setting
CLK_PWRGD 16
C454 33P/50V_4
2
Layout Note:
XTAL length < 500mils Y10
14.318MHZ
Add capacitor pads for improving WWAN.
1
C455 33P/50V_4
R770 22/F_4 C462 *27P/50V_4@NC CLK_ICH_48M
29 CLK48_7412
C755 *27P/50V_4@NC CLK_SIO_14M CPU Clock select
R712 22/F_4 C756 *27P/50V_4@NC CLK_ICH_14M FSC FSB FSA CPU SRC PCI
B 16 CLK_ICH_48M B
R359 2.2K_4 C759 *27P/50V_4@NC PCI_CLK_8512 1 0 1 100 100 33
3,6 CPU_MCH_BSEL0
C459 *27P/50V_4@NC PCLK_7412
3,6 CPU_MCH_BSEL1
C450 *27P/50V_4@NC PCLK_LPC_DEBUG 0 0 1 133 100 33
R631 10K_4 C453 *27P/50V_4@NC CLK_PCI_TPM
3,6 CPU_MCH_BSEL2
C761 *27P/50V_4@NC CLK_PCI_ICH 0 1 1 166 100 33
R625 15_4
16 CLK_ICH_14M
R624 15_4
0 1 0 200 100 33
37 CLK_SIO_14M
0 0 0 266 100 33
add R712 and R770 1 0 0 333 100 33
remove R363 1 1 0 400 100 33
for TI7412 change 1 1 1 RSVD 100 33
Mika 2006/11/30
R770 R712 change value from 15 to 12.1 GCLK_SEL = FCTSEL1
(CS01212FB14) FCTSEL1 PIN13 PIN14 PIN17 PIN18
Mika 2007/01/05 (PIN6)
0=UMA DOT96T DOT96C SRCT1/LCDT_100 SRCC1/LCDT_100
R770 R712 change value from 12.1 to 22
(CS02202FB12) 1 = External
A VGA SRCT0 SRCC0 27Mout-NSS 27Mout-SS A
Mika 2007/03/02
PROJECT : TA7
Quanta Computer Inc.
Size Document Number Rev
Clock Gen 2A
Date: Friday, March 02, 2007 Sheet 2 of 49
5 4 3 2 1
5 4 3 2 1
H_A#[3..16] U30A
5 H_A#[3..16]
H_A#3 J4 H1
CPU Thermal monitor
A[3]# ADS# H_ADS# 5
ADDR GROUP 0
H_A#4 L5 E2
CPU(HOST) H_A#5 L4
A[4]# BNR#
G5
H_BNR# 5 19 THCLK_SMB
19 THDAT_SMB
A[5]# BPRI# H_BPRI# 5
H_A#6 K5
H_A#7 A[6]#
M3 A[7]# DEFER# H5 H_DEFER# 5
H_A#8 N2 F21 +3.3V +3.3V
A[8]# DRDY# H_DRDY# 5
H_A#9 J1 E1 Q47
A[9]# DBSY# H_DBSY# 5
2
H_A#10 N3 2N7002W-7-F R565 220_6 6648VCC
H_A#11 A[10]#
P5 A[11]# BR0# F1 H_BR0# 5
H_A#12 P2 ABCLK 3 1 THCLK_SMB C693
16,35,42 ABCLK
CONTROL
H_A#13 A[12]#
L2 A[13]# IERR# D20 H_IERR# R187 56.2/F_4 +1.05V_VCCP R566 R563 R553
R558
H_A#14 P4 B3 *10K_4@NC 0.1U/10V/X5R_4
A[14]# INIT# H_INIT# 14
H_A#15 P1 10K_4 10K_4 10K_4
H_A#16 A[15]# +3.3V U34
R1 A[16]# LOCK# H4 H_LOCK# 5
D Q45 D
5 H_ADSTB#0 M1 ADSTB[0]#
2
H_REQ#[0..4] C1 H_RESET# 2N7002W-7-F 8 1
5 H_REQ#[0..4] RESET# H_RESET# 5 SCLK VCC
H_REQ#0 K3 F3 H_THERMDA
REQ[0]# RS[0]# H_RS#0 5
H_REQ#1 H2 F4 ABDATA 3 1 THDAT_SMB 7 2
REQ[1]# RS[1]# H_RS#1 5 16,35,42 ABDATA SDA DXP
H_REQ#2 K2 G3
REQ[2]# RS[2]# H_RS#2 5
H_REQ#3 J3 G2 R554 *0_4@NC 6 3 C248
REQ[3]# TRDY# H_TRDY# 5 16 THERM_ALERT# ALERT# DXN
H_REQ#4 L1 2200P/50V/X7R_6
H_A#[17..35] REQ[4]# +3.3V H_THERMDC
5 H_A#[17..35] HIT# G6 H_HIT# 5 4 OVERT# GND 5
H_A#17 Y2 E4
A[17]# HITM# H_HITM# 5
2
H_A#18 U5 Q46
H_A#19 A[18]# ITP_BPM#0 2N7002W-7-F G781P8
R3 A[19]# BPM[0]# AD4 T12 Default PU 56ohm if no
ADDR GROUP 1
H_A#20 W6 A[20]# BPM[1]# AD3 ITP_BPM#1 T10 43 SYS_SHDN# 3 1 6648OVERT# ADDRESS: 98H
H_A#21 ITP_BPM#2 use.Serial R NC
XDP/ITP SIGNALS
U4 A[21]# BPM[2]# AD1 T13
H_A#22 Y5 AC4 ITP_BPM#3 T9 If connect to power side Layout Note:
H_A#23 A[22]# BPM[3]# ITP_BPM#4
U1 AC2 T8 Layout Note:Routing 10:10 mils and
H_A#24 R4
A[23]# PRDY#
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