Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_Z07
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5 4 3 2 1
Z07 SYSTEM BLOCK DIAGRAM 01
DDRII-SODIMM1 VCC_CORE
+1.8VSUS HOST 200MHz CPU CORE
D
+SMDDR_VREF PG 8,9 DDR II 667 MHZ AMD S1g1 D
Athlon Rev.F/G Dual-Core 31W/35W PCIE 100MHz +NB_CORE NB CORE
DDRII-SODIMM2
CLOCK GENERATOR
USB 48MHz (1.0~1.2V)
+1.8VSUS (638 S1g1 socket)
+SMDDR_VREF PG 8,9 +2.5V
+1.2V REF 14.318MHz +2.5V
+2.5V
+1.8VSUS
CPU THERMAL VCC_CORE PG 4,5,6,7 HTREF 66MHz
+SMDDR_VTERM +3V PG 3 +1.5V
SENSOR +1.5V
HT_LINK(1.0)
+3.3V PG 6
800 MHZ +1.2V
+1.2V_S5 +1.2V
LAN(10/100/1000)
PCIE
BCM5784M RJ45
+1.8VSUS
LVDS(1ch)
NB +3V_S5 PG 21 PG 21
LVDS Panel(LED) +1.8V +1.8VSUS
+3V
VIN PG 19
RS690MC +SMDDR_VTERM SMDDR
465 FCBGA
C
PCIE +SMDDR_VREF C
Mini Card (WLAN)
+1.2V +1.5V
CRT +1.8V +3V PG 22
+3V +3V PG 10,11,12,13 +3VPCU
+5V PG 18 +NB_CORE
+3V_S5
+3VSUS
A_LINK (X4) 3V/5V
BT CONN. +3V
+3VSUS PG 22 +5VPCU
SATA - HDD1 SATA0 +5V
+3V
+5V PG 24 Card Reader controller Card Reader
+3V
RTS5159E
PG 23 PG 23
SATA - ODD SATA1
SB
+5V PG 24
SB600 USB2.0 USB2.0 I/O Ports X1
549 BGA +5VPCU PG 25
B B
Azalia +1.2V
+1.2V_S5
Azalia Audio Codec +1.8V
CX20561-15z +3V_S5
PG 20 +3V
+3V +5V PG 14,15,16,17
VCCRTC
MODEM CONN. LPC WEBCAM
+3V PG 19
(MDC)
HP+SPDF MIC AMP +3.3V_SUS PG 24
JACK JACK G1441
+5V +3V
EC
PG 20 PG 20 PG 20
+5V WIRE WPCE775
+3V
+3VPCU PG 26
USB X 2
Speaker Board to
board CONN. SPI
A
PG 20 A
PG 24
POWER/B Flash Touch MMB/B
FAN Keyboard
PG 25 ROM Pad +3V
PG 25 PROJECT : 14" Z07
+3VPCU
PG 6 PG 26 +5V
PG 26 PG 25
+3VPCU Quanta Computer Inc.
Size Document Number Rev
BLOCK DIAGRAM 1A
Date: Tuesday, March 10, 2009 Sheet 1 of 36
5 4 3 2 1
5 4 3 2 1
2
Z07 Power On Sequence CPU HOLE
From AC,Battery VIN
HOLE6 HOLE4 HOLE7 HOLE3
+5VPCU +3VPCU *h-ts315bs256d169p2 *h-ts315bs256d169p2*h-ts315bs256d169p2*h-ts315bs256d169p2
D D
From PWM SYS_HWPG(PCU)
1
1
1
1
From Power Button NBSWON#
From EC S5_ON
+5V_S5 HOLE1 HOLE5 HOLE9 HOLE10
H-TC315BC236D142P2 H-TC315BC236D142P2 H-TC315BC236D142P2 *h-ts315bs256d169p2
+3V_S5
1
1
1
1
+1.2V_S5 >10ms
From EC RSMRST# >100ms HOLE11 HOLE15 HOLE13 HOLE12
*h-ts315bs256d169p2*h-ts315bs256d169p2 *h-ts315bs256d169p2*h-ts315bs256d169p2
From EC DNBSWON#
From SB PCIE_WAKE#
1
1
1
1
From SB to EC SUSB#,SUSC# SUSON
From EC SUSON HOLE14 HOLE18 HOLE16 HOLE19
*h-ts315bs256d169p2*h-ts315bs256d169p2 *h-ts315bs256d169p2*h-ts315bs256d169p2
+3VSUS +1.8VSUS SMDDR_VREF
1
1
1
1
From PWM HWPG_1.8V (SUS) MAINON
C From EC MAINON C
HOLE17
*h-ts315bs256d169p2 HOLE8
+5V +3V +2.5V +1.8V +1.5V SMDDR_VTERM *h-ts315bs256d169p2
From PWM HWPG_1.5V,HWPG_2.5V,GFXPG(MAIN)
1
1
MAINON
From EC VRON
HOLE20
*h-ts315bs256d169p2
+VCC_CORE
From PWM CPU_PWRGD
1
MAINON+RC
From EC +1.2V_ON
From EC +1.2V
From PWM HWPG_CPUIO +1.2V_ON+RC
From EC +1.2V_ON+RC
From EC +NB_CORE
From PWM HWPG_1.2_NB
HWPG
From EC ECPWROK
B
NB_PWRGD -22ms~500ms
B
SB_PWRGD 47ms~66ms
From SB CPU_PWRGD 71ms~73ms
From SB PLTRST# PCIRST# 1.9ms~2.1ms
From SB CPU_LDT_RST#
From SB CPU_LDT_STOP#
*Note: EC will sampling SUSB# &
SUSC# every 5ms.
AMD SB600 SMBUS Table EC SMBUS Table
CLK GEN RAM Mini Card (HD-Decoder) Mini-card(WL) New Card HDMI Battery CPU thermal Sensor EC EEPROM VGA thermal Sensor Touch Sensor HDMI CEC
SB600 SDATA0/SCLK0(+3V) V V V V V EC775 SDATA1/SCLK1(+3VPCU) V
SB600 SDATA0/SCLK0(+3V_S5) V EC775 SDATA2/SCLK2(+3VPCU) V V
Power +3V +3V +3V +3V (Atheros) +3V +3V_S5 EC775 SDATA3/SCLK3(+3VPCU) V V V
A A
Reserve MOS ckt V V V V V V EC775 SDATA4/SCLK4(+3VPCU)
Power +3VPCU +3V +3VPCU +3V +3VPCU +5VPCU
Reserve MOS ckt X V X V X V
PROJECT : Z07
Quanta Computer Inc.
Size Document Number Rev
SYSTEM INFORMATION 3C
Date: Tuesday, March 10, 2009 Sheet 2 of 36
5 4 3 2 1
5 4 3 2 1
+3V
L23 BK1608HS600_6
CLK_VDD
Put Decoupling Caps close to Clock Gen. power pin
CLK_VDDA L17
+3V
BK1608HS600_6
3
C219 C521 C203 C206 C207 C243 C202 C204 C518 C197 C199
22U/6.3V_8 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 0.1u/10V_4 10u/10V_8
D D
+3V
CLK_VDD
L25 BK1608HS600_6 CLK_VDD_USB U6
54 50 CLK_VDDA
C234 C233 VDDCPU VDDA R154 261/F_4
14 49
1u/6.3V_4 *0.1u/10V_4 VDD_SRC1 GNDA
23
28 VDD_SRC2 56 CPUCLK_EXT_R R161 47.5/F_4
VDD_SRC3 CPUCLK8T0 CPUCLKP 6
44 55 CPUCLK#_EXT_R R162 47.5/F_4
+3V VDD_SRC4 CPUCLK8C0 CPUCLKN 6
CLK_VDD_USB 5 52 T63
VDD_48 CPUCLK8T1
39
VDD_ATIG CPUCLK8C1
51 T60 Don't add them when use RTM870T-690
L24 BK1608HS600_6 CLK_VDD_REF CLK_VDD_REF 2
VDD_REF SBLINK_CLKP_R
60 16 3 4 SBLINK_CLKP 12
C228 VDDHTT SRCCLKT6 RP17
17 SBLINK_CLKN_R 1 2 33X2 SBLINK_CLKN 12
C230 SRCCLKC6 NBSRC_CLKP_R
53 41 1 2 NBSRC_CLKP 12
2.2u/6.3V_6 *0.1u/10V_4 GND_CPU ATIGCLKT0 RP15
15 40 NBSRC_CLKN_R 3 4 33X2 NBSRC_CLKN 12
22 GND_SRC1 ATIGCLKC0 37
GND_SRC2 ATIGCLKT1 T59
29 36 T55
GND_SRC3 ATIGCLKC1
45 35 T56
8 GND_SRC4 ATIGCLKT2 34
GND_48 ATIGCLKC2 T57
C239 22p_4 38 30 T69
CLK_VDD GND_ATIG ATIGCLKT3
C 1 31 T66 C
2
58 GND_REF ATIGCLKC3 18
GNDHTT SRCCLKT5 T67
Y2 R190 19 T70
R188 14.318MHZ_20pF *1M_4 CLK_XIN 3 SRCCLKC5 20
XIN SRCCLKT4 T71
21 T68
1
10K_4 C240 22p_4 CLK_XOUT 4 SRCCLKC4 24 GPP_CLK1P_R 3 4
XOUT SRCCLKT3 SBSRCCLKP 14
25 GPP_CLK1N_R RP18 1 2 33X2 SBSRCCLKN 14
SRCCLKC3 GPP_CLK2P_R
26 3 4
Parallel Resonance Crystal SRCCLKT2
27 GPP_CLK2N_R RP19 1 2 33X2
CLK_PCIE_WLAN
CLK_PCIE_WLAN#
22
22
SRCCLKC2
11 47 T62
T64 RESET_IN# SRCCLKT0
61 46 T61
NC SRCCLKC0 43
SRCCLKT1 T54
42 T58
SRCCLKC1 12 GPP_CLK0P_R 3 4 CLK_PCIE_LAN 21
SRCCLKT7 GPP_CLK0N_R
13 1 2 CLK_PCIE_LAN# 21
SRCCLKC7 RP16 33X2
Clock Gen I2C
CGCLK_SMB 9 57 CLKREQA#
SMBCLK CLKREQA#
CGDAT_SMB 10
SMBDAT CLKREQB#
32 CLKREQB# Don't add them when
R200
R199
R193
R198
R195
R194
R150
R149
R197
R196
R196
33 +3V
CLKREQC# T65 use RTM870T-690
+3V 48 7 CLK_48M_1_R R186 33_4
IREF 48MHz_1 CLK_Card48 23
Ioh = 5 * Iref 6 CLK_48M_2_R Q24
48MHz_0 R185 33_4 R178 *RHU002N06
(2.32mA) USBCLK 15
2
Q26 R163
*RHU002N06 R187 Voh = 0.71V @ 60 ohm 475/F_4 63 *10K_4
2
FS1/REF1
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
49.9/F_4
64 CLKREQB# 1 3
FS0/REF0 CLKREQ_WLAN# 22
*10K_4 62
CGCLK_SMB FS2/REF2
8,15,21,22 SCLK0 3 1 59
HTTCLK0
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