Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_Z09
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download Quanta_Z09 documenatation <<
Text preview - extract from the document
5 4 3 2 1
VER : 3A
BOM P/N Description Z09 SYSTEM BLOCK
DIAGRAM
D D
Dual Channel DDR III
Memory Down 1333/1600 MHZ
DDRIII-SODIMM1 IMC NVIDIA GPU
P13 PCI-E
PCIE
Ivy Bridge X16 N13P-GV
1GB (128Mb x 32 IO x 4 pcs)
256MB*16 2.5GT/s
BGA 1023
P27,28,29,30,31,32
17W
P2,3,4,5,6 X'TAL
27.0MHz
Max. 2G P14
eDP eDP Conn.
mSATA - HDD FDI DMI P15
P20
DMI(x4)
SATA - HDD FDI DMI
SATA
P20
C C
SATA - ODD SATA
P21 Display
HDMI
HDMI Conn.
USB3.0(USB2.0) P16
USB3.0 *2
USB2.0 *2
USB Port
P23
USB3.0(USB2.0) PCIE-8
USB3.0
USB Port Panther Point PCI-E x1 MINI CARD
P23 WLAN+BT
USB-10 P19
PCI-E x1 PCH
BGA 989 PCI-E x1
BCM57780
USB Port P7, 8, 9, 10, 11, 12 PCIE-3 RJ45 Conn.
(Charger)P23 GIGA LAN P18
P17
X'TAL
USB2.0 32.768KHz X'TAL
25MHz
B B
USB2.0
CCD Conn. USB2.0
X'TAL
P15 25MHz
PCIE-2 RTS5209-GR Cardreader
Cardreader Conn.(2in1)
P8 BATTERY RTC
controller P19
SPI
SPI ROM
Azalia IHDA P8
Daugther board
LPC
2M+4M
LPC
Batery Charger P31 +1.05V P34 +VGFX_AXG P33
ALC271-VB6 WPCE885
DMIC
AUDIO CODEC EC
Daugther board P19 P24 3V/5V P32 +1.8V/+1V P37 CPU core P33
Discharger
+VGPU_CORE P38 +VGPU_IO P38 P37
BOM Option Table
A A
MIC/HP JACK K/B Con. Touch Pad
Reference Description Con.
P22 P19 Thermal Protection
EV@ Optimize SKU
P37
SNB@ For Sandy bridge.
IVB@ For Ivy bridge.
IV@ For UMA. W25X16VSS1G EM-6781-T3 Fan Driver Quanta Computer Inc.
Speaker HALL SENSOR
* do not stuff SPI FLASH P8 P15 P19 PROJECT : Z09
Size Document Number Rev
3A
Block Diagram
Date: Monday, April 09, 2012 Sheet 1 of 40
5 4 3 2 1
5 4 3 2 1
Ivy Bridge Processor (DMI,PEG,FDI)
PEG_ICOMPI and RCOMPO signals
should be shorted and routed with
- max length = 500 mils
U9A - typical impedance = 43 mohms
G3 PEG_COMP PEG_ICOMPO 12mil PEG_ICOMPO signals should be routed with
PEG_ICOMPI G1
M2 PEG_ICOMPO G4 PEG_ICOMPI, PEG_RCOMPO 4mil, - max length = 500 mils
<7> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO - typical impedance = 14.5 mohms
P6
<7> DMI_TXN1 DMI_RX#[1]
<7> DMI_TXN2 P1 GRN[0..15] <25>
P10 DMI_RX#[2] H22 GRN15
D <7> DMI_TXN3 DMI_RX#[3] PEG_RX#[0] D
J21 GRN14
N3 PEG_RX#[1] B22 GRN13
<7> DMI_TXP0 DMI_RX[0] PEG_RX#[2]
P7 D21 GRN12
<7> DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI
<7> DMI_TXP2 P3 A19 GRN11
P11 DMI_RX[2] PEG_RX#[4] D17 GRN10
<7> DMI_TXP3 DMI_RX[3] PEG_RX#[5] B14 GRN9
K1 PEG_RX#[6] D13 GRN8
<7> DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
M8 A11 GRN7
<7> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
<7> DMI_RXN2 N4 B10 GRN6
R2 DMI_TX#[2] PEG_RX#[9] G8 GRN5
<7> DMI_RXN3 DMI_TX#[3] PEG_RX#[10] A8 GRN4
K3 PEG_RX#[11] B6 GRN3
<7> DMI_RXP0 DMI_TX[0] PEG_RX#[12]
M7 H8 GRN2
<7> DMI_RXP1 DMI_TX[1] PEG_RX#[13]
<7> DMI_RXP2 P4 E5 GRN1
T3 DMI_TX[2] PEG_RX#[14] K7 GRN0
<7> DMI_RXP3 DMI_TX[3] PEG_RX#[15]
GRP[0..15] <25>
K22 GRP15
PEG_RX[0] K19 GRP14
PEG_RX[1] C21 GRP13
U7 PEG_RX[2] D19 GRP12
<7> FDI_TXN0 FDI0_TX#[0] PEG_RX[3]
W11 C19 GRP11
<7> FDI_TXN1 FDI0_TX#[1] PEG_RX[4]
<7> FDI_TXN2 W1 D16 GRP10
PCI EXPRESS -- GRAPHICS
AA6 FDI0_TX#[2] PEG_RX[5] C13 GRP9
<7> FDI_TXN3 FDI0_TX#[3] PEG_RX[6]
<7> FDI_TXN4 W6 D12 GRP8
V4 FDI1_TX#[0] PEG_RX[7] C11 GRP7
<7> FDI_TXN5 FDI1_TX#[1] PEG_RX[8]
Y2 C9 GRP6
<7> FDI_TXN6 FDI1_TX#[2] PEG_RX[9]
Intel(R) FDI
<7> FDI_TXN7 AC9 F8 GRP5
FDI1_TX#[3] PEG_RX[10] C8 GRP4
PEG_RX[11] C5 GRP3
C U6 PEG_RX[12] H6 GRP2 C
<7> FDI_TXP0 FDI0_TX[0] PEG_RX[13]
W10 F6 GRP1
<7> FDI_TXP1 FDI0_TX[1] PEG_RX[14]
<7> FDI_TXP2 W3 K6 GRP0
AA7 FDI0_TX[2] PEG_RX[15]
<7> FDI_TXP3 FDI0_TX[3] GTN[0..15] <25>
<7> FDI_TXP4 W7 G22 GTN15C C154 [email protected]/10V_4 GTN15
T4 FDI1_TX[0] PEG_TX#[0] C23 GTN14C C152 [email protected]/10V_4 GTN14
<7> FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
AA3 D23 GTN13C C149 [email protected]/10V_4 GTN13
<7> FDI_TXP6 FDI1_TX[2] PEG_TX#[2]
<7> FDI_TXP7 AC8 F21 GTN12C C148 [email protected]/10V_4 GTN12
FDI1_TX[3] PEG_TX#[3] H19 GTN11C C146 [email protected]/10V_4 GTN11
AA11 PEG_TX#[4] C17 GTN10C C143 [email protected]/10V_4 GTN10
<7> FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
AC12 K15 GTN9C C142 [email protected]/10V_4 GTN9
<7> FDI_FSYNC1 FDI1_FSYNC PEG_TX#[6] F17 GTN8C C140 [email protected]/10V_4 GTN8
U11 PEG_TX#[7] F14 GTN7C C137 [email protected]/10V_4 GTN7
<7> FDI_INT FDI_INT PEG_TX#[8] A15 GTN6C C136 [email protected]/10V_4 GTN6
AA10 PEG_TX#[9] J14 GTN5C C156 [email protected]/10V_4 GTN5
<7> FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10]
AG8 H13 GTN4C C134 [email protected]/10V_4 GTN4
<7> FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11] M10 GTN3C C162 [email protected]/10V_4 GTN3
PEG_TX#[12] F10 GTN2C C132 [email protected]/10V_4 GTN2
PEG_TX#[13] D9 GTN1C C130 [email protected]/10V_4 GTN1
PEG_TX#[14] J4 GTN0C C128 [email protected]/10V_4 GTN0
AF3 PEG_TX#[15]
eDP_ICOMPO 12mil EDP_COMP AD2 eDP_COMPIO F22 GTP15C C153 [email protected]/10V_4 GTP15
GTP[0..15] <25>
eDP_COMPIO 4mil INT_EDP_HPD# AG11 eDP_ICOMPO PEG_TX[0] A23 GTP14C C151 [email protected]/10V_4 GTP14
eDP_HPD PEG_TX[1] D24 GTP13C C150 [email protected]/10V_4 GTP13
PEG_TX[2] E21 GTP12C C147 [email protected]/10V_4 GTP12
EDP_AUX# AG4 PEG_TX[3] G19 GTP11C C145 [email protected]/10V_4 GTP11
<15> EDP_AUX# AF4 eDP_AUX# PEG_TX[4] B18
EDP_AUX GTP10C C144 [email protected]/10V_4 GTP10
<15> EDP_AUX eDP_AUX PEG_TX[5] K17 GTP9C C141 [email protected]/10V_4 GTP9
PEG_TX[6]
DP
G17 GTP8C C139 [email protected]/10V_4 GTP8
EDP_TX0# AC3 PEG_TX[7] E14 GTP7C C138 [email protected]/10V_4 GTP7
B <15> EDP_TX0# eDP_TX#[0] PEG_TX[8] B
AC4 C15 GTP6C C135 [email protected]/10V_4 GTP6
AE11 eDP_TX#[1] PEG_TX[9] K13 GTP5C C155 [email protected]/10V_4 GTP5
AE7 eDP_TX#[2] PEG_TX[10] G13 GTP4C C133 [email protected]/10V_4 GTP4
eDP_TX#[3] PEG_TX[11] K10 GTP3C C161 [email protected]/10V_4 GTP3
EDP_TX0 AC1 PEG_TX[12] G10 GTP2C C131 [email protected]/10V_4 GTP2
<15> EDP_TX0 eDP_TX[0] PEG_TX[13]
AA4 D8 GTP1C C129 [email protected]/10V_4 GTP1
AE10 eDP_TX[1] PEG_TX[14] K4 GTP0C C127 [email protected]/10V_4 GTP0
AE6 eDP_TX[2] PEG_TX[15]
eDP_TX[3]
SNB_2CBGA_1P0 0.22uF AC coupling Caps for PCIE GEN1/2/3
DG 1.0 :
The recommended AC cap value is changed to 220nF for compatibility with
DP_COMPIO and ICOMPO signals PCIe Gen3 on future platforms.
should be shorted near balls and routed with For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.
- typical impedance < 25 mohms
+1.05V_VTT
DP & PEG Compensation eDP Hot-plug (Disable)
20111104 change from 10k to 1k.
R192
+1.05V_VTT 1K_4
A INT_EDP_HPD# A
EDP_COMP R564 24.9/F_4
3
+1.05V_VTT 2 EDP_HPD
EDP_HPD <15>
Q2
Quanta Computer Inc.
PEG_COMP
CAD Note: Place PU resistor
R193 24.9/F_4 2N7002E R191
within 2 inches of CPU PROJECT : Z09
1
100K_4 Size Document Number Rev
3A
HPD PU/PD resistor values based Ivy Bridge 1/5
on CRB and different to DG Date: Monday, April 09, 2012 Sheet 2 of 40
5 4 3 2 1
5 4 3 2 1
Boot S3 S3 RSM
+1.5V_CPU
DRAM_PWRGD
Ivy Bridge Processor (CLK,MISC,JTAG) 100 ns after +1.5V_CPU
SYS_PWROK reaches 80%
U9B
D SM_DRAMPWROK D
J3 CLK_CPU_BCLKP <9>
BCLK H2 CLK_CPU_BCLKN <9>
CLOCKS
BCLK#
MISC
If motherboard only supports external graphics or if it supports
F49 TP95
20111121 Remove R5306/R5311/R5474/R5476. Processor Graphics but without eDP:
<8> H_SNB_IVB# PROC_SELECT# Connect DPLL_REF_SSCLK on Processor to GND through 1K +/-
AG3 CLK_DPLL_SSCLKP <9>
DPLL_REF_CLK AG1 5% resistor.
DPLL_REF_CLK# CLK_DPLL_SSCLKN <9> Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/
TP85 C57 TP53 - 5% resistor
PROC_DETECT#
N59 CLK_PCIE_XDPP_R R230 *0_4 CLK_PCIE_XDPP <9>
BCLK_ITP N58 CLK_PCIE_XDPN_R R229 *0_4
BCLK_ITP# CLK_PCIE_XDPN <9>
TP78 TP_CATERR# C49
CATERR#
THERMAL
Isolate Space:20mils
A48 AT30
<10,24> EC_PECI PECI SM_DRAMRST# CPU_DRAMRST# <4,24>
BF44 SM_RCOMP_0 R209 140/F_4 CAD NOTE: All DDR_COMP signals
R207 56_4 H_PROCHOT#_R C45 SM_RCOMP[0] BE43 SM_RCOMP_1 R206 25.5/F_4 should be routed such that :-
<24,33> H_PROCHOT#
DDR3
MISC
C253 PROCHOT# SM_RCOMP[1] BG43 SM_RCOMP_2 R204 200/F_4 - max length = 500 mils
2 1 *43P/50V_4N SM_RCOMP[2] - trace width = 15mils and
- MB trace impedance < 68 mohms
(worst case resistance)
D45 Impedance 85ohm
<10> PM_THRMTRIP# THERMTRIP#
N53 TP79
PRDY# N55 XDP_PREQ#
PREQ# TP83
C C
L56 XDP_TCLK_VT <8,22> Place near to XDP connector
TCK L55
Over 130 degree C will TMS XDP_TMS_VT <8,22>
PWR MANAGEMENT
J58 XDP_TRST# TP103
drive low
JTAG & BPM
TRST# 51_4 R232 PCH_XDP_TDO_VT
+1.05V_VTT
<7> PM_SYNC R214 *SHORT_4 PM_SYNC_R C48 M60 XDP_TDI_VT <22>
PM_SYNC TDI L59
TDO PCH_XDP_TDO_VT <8>
C718 0.1U/10V_4
20111021 Add 10k to +3V,CRB 1k
R596 *SHORT_4 H_PWRGOOD_R B46 20111103 del R601
<10> H_PWRGOOD UNCOREPWRGOOD K58 XDP_DBRST#_R R233 0_4 XDP_DBRST# <7>
R595 10K_4 DBR#
PM_DRAM_PWRGD_R BE45 G58 Option for Prochot# function +1.05V_VTT
Isolate Space:20mils SM_DRAMPWROK BPM#[0] E55
TP97
BPM#[1] TP82 68 ohm for unused, 62 ohm for used
E59
BPM#[2] TP81
R194 75/F_4 G55 H_PROCHOT# R219 62_4
+1.05V_VTT TP67 BPM#[3] TP80
G59
BPM#[4] TP98
CPU_PLTRST# R190 43_4 CPU_PLTRST#_R D44 H60 TP100
RESET# BPM#[5] J59 XDP_TMS_VT R606 51_4
BPM#[6] TP99
J61 XDP_TDI_VT R231 51_4
BPM#[7] TP101
R196 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo