Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_ZN2-0316
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8 7 6 5 4 3 2 1
1
Schematic Page Description :
D D
01 -- Page Description 19 -- PCH 1/6 (DMI/FDI/VIDEO) 39 -- ADP AC IN & HDD12V
02 -- System Block Diagram 20 -- PCH 2/6(SATA/RTC/HDA/LPC) 41 -- V_AXG (ISL6314)
03 -- Power Map 21 -- PCH 3/6(PCIE/USB/CLK/NV) 42 -- DDR3 1.5V(TPS51116)
04 -- Power Sequence 1/2 22 -- PCH 4/6(GPIO/CPU) 43 -- CPU_VTT(ISL6314CRZ)
05 -- Power Sequence 2/2 23 -- PCH 5/6(POWER) 44 -- CPU_CORE (NCP5392)
06 -- Clock 24 -- PCH 6/6(GND) 45 --1.05V_PCH, 1.05V_ME,1.8V
07 -- SMBus Block Diagram 25 -- MXM 3.0 46 -- Discharge Circuit
C C
08 -- GPIO list 26 --AUDIO CODEC ALC269 47 -- CHANGE LIST1
09 -- CLOCK GENERATOR 27 --LINE OUT/CRT 48 -- CHANGE LIST2
10 -- MCP 1/7(CLK/CTRL/MISC) 28 --JMB380 (Card Reader/1394) 49 -- ANNOTATIONS
11 -- MCP 2/7(DDR3 CHANNEL A) 29 -- SATA HDD/ODD
12 -- MCP 3/7(DDR3 CHANNEL B) 30 --MINI PCIE(WLAN/TV/IR/BT)
13 -- MCP 4/7(PCIE/DMI) 31 --ON BOARD USB
14 -- MCP 5/7( VCCP) 32 --LCD PANEL/INVERTER
15 -- MCP 6/7(MISC/VCC) 33 --LAN(RTL8111DL)
B B
16 -- MCP 7/7(GND) 34 --LAN Transformer & RJ45
17 -- DDR3 CHA DIMM0 35 --FAN/D board/CCD/PS2
18 -- DDR3 CHB DIMM0 36 -- EC ITE 8512N/FLASH
37 -- XDP
38 -- SCREW HOLE
A A
Quanta Computer Inc.
PROJECT : ZN2
Size Document Number Rev
A
Page Description
Date: Tuesday, March 16, 2010 Sheet 1 of 49
8 7 6 5 4 3 2 1
5 4 3 2 1
Block Diagram :
D D
VRM 11.1 Channel A DDR3 DIMM
CPU Core Lynnfield/ SO-DIMM0 CLOCK Generator
NCP5392 Clarkdale Dual channel DDR3 CK505
800/1066/1333MHz 1.5V
Processor Channel B DDR3 DIMM 14.318MHz
SO-DIMM1
MXM CNN (Graphics) 64-bit/45nm Reset Circuit
Mobile PCI-E Module PCIE 2.0 x16(PEG) LGA1156
TYPE-A (314 pin) (37.5x37.5mm) LED Indicator
(95W) VTT_CPU
1.1V MAIN SW CNN
LVDS
LCD Panel CNN FDI PECI DMI
AUO/CHIMEI (*1) x4
(21'' 16:10)
C Converter From EC 25MHz C
Backlight control
ADPIN LCD Panel CNN
CNN AUO/CHIMEI LVDS Ibex Peak PCI-E x1 PCIE 3 GB LAN RJ45 CNN
System Power (21'' 16:10) (Non-MXM option) Realtek
ADPIN
VIN
PCH RTL8111DL
6 in 1
+5VPCU/+3VPCU
MAINON CARD READER CNN
12VCC SATA HDD(3.5") SATA 0 PCIE 5
SATA II QLLT1071
GFX_VR_EN V_AXG
DCIN/VIN (25x25mm) (JMICRO JMB385)
SUSON SATA ODD SATA 1
+1.5V_SUS
MAINON (3.5W)
CPU_VTT_1.1V PCIE 1 Mini PCIE1
VRON REAR USB x4 USB 0,1,8,11
+VCC_CORE USB 2.0 USB 5 WLAN CNN
USB 2.0
S5_PWRON +5V_S5 USB 2,3
SIDE USB x2
SUSD +5V_S5_USB
B
+5VPCU USB Dongle x1 USB 9
PCIE 2 Mini PCIE2 B
MAIND +5V
USB 12 TV Tuner CARD CNN
S5_PWRON +3V_S5 USB 4
CAREMA with
MIC RTC
+3VPCU MAIND +3V Battery
BLUE TOOTH USB 10 Annt.
MAINON +1.8V 8Mb SPI
+5V_S5 32.768KHz SPI Ignition
LPC FW
MAINON +1.05V
+1.5V_SUS
AUDIO CODEC EC/KBC
ALC269Q Azailia 32.768KHz
INT SPK AMP. LQFP48 ITE8512
CNN(2Wx2) LQFP128
INT MIC Head MIC Line
On WCM Phone IN Out FAN CTRL 2Mb SPI IR IR
A
(CPU/ BIOS RECEIVER Blaster A
System) ROM
Quanta Computer Inc.
PROJECT : ZN2
(*1)FDI - Used only for the Clarkdale processor. Size Document Number Rev
A
Block Diagram
Date: Tuesday, March 16, 2010 Sheet 2 of 49
5 4 3 2 1
5 4 3 2 1
Power Rail Destination Voltage S0 Current
VIN 3
+12V
+VCC_CORE Lynnfield : 0.65V~1.4V MAINON
90A(TDC)
Default for initial power up 1.1V
for 92W TDP SKU 10A (TDC)
0.5~1.3V
V_AXG for 79W TDP SKU 16A (TDC) Adaptor NCP1587
D
+1.1V_VTT Lynnfield : Memory controller 1.045V~1.1V~1.155V 30A(TDC) S5_Power_ON D
& shared cache
Ibex Peak : DMI 1.1V 0.065A
Ibex Peak : CPU_IO 1.05V~1.1V~1.16V 0.001A MOS
G
+5V_S5
Lynnfield : Internal processor PLL 1.71V~1.8V~1.89V 1.1A
D
S
+1.8V
Ibex Peak : Internal PLL & VRMs 1.71V~1.8V~1.89V 0.196A
Ibex Peak : Dual channel NAND I/F 1.71V~1.8V~1.89V 0.156A
+1.5V_SUS Lynnfield : CPU I/O Voltage for DDRIII 1.425V~1.5V~1.575V 6A MAINON
DIMM : +5VPCU
SMDDR_VTERM DDRIII Terminator: 0.75V 2A MOS +5V
G
D
S
+1.05V Ibex Peak : VccCore 0.998V~1.05V~1.1V 1.629A
Ibex Peak : Vcc core I/O buffer 0.998V~1.05V~1.1V 3.251A
Ibex Peak : DMI buffer voltage 0.998V~1.05V~1.1V 0.065A
Ibex Peak : Display PLL A power 0.998V~1.05V~1.1V 0.075A
Ibex Peak : Display PLL B power 0.998V~1.05V~1.1V 0.075A NCP1587
S5_Power_ON
+1.5V Mini PCIE : +1.5V(WLAN)
MOS
G
C +3V_S5 C
D
S
+3V
Ibex Peak : I/O buffer voltage 3.14V~3.3V~3.47V 0.357A MAINON +3V
Ibex Peak : Display DAC Analog power 3.14V~3.3V~3.47V 0.069A
CH7308 : LVDD
+3VPCU
ALC662 : DVDD
MOS LDO
G
Mini PCIE : +3.3V(WLAN) D +1.8V
G
CAREMA
D
S
OP
S
+1.5V_SUS
MAINON SUSON MAINON +1.5V
Ibex Peak : Core well Ref. voltage 4.75V~5V~5.25V 0.001A
SATA ODD
SATA HDD(2.5'' x SSD)
ALC662S : AVDD
LDO +1.05V
G
G D
Touch Screen TPS51116RGE OP
D
S
+5V LCD Panel S
USB: x 12 ports 5V 6A
B SMDDR_VTERM B
MXM_12V
HDD_12V
Ibex Peak : Intel Management Engine 3.14V~3.3V~3.47V 0.086A
+3V_S5 +1.1V_VTT
Ibex Peak : Suspend well I/O Buffer 3.14V~3.3V~3.47V 0.168A
Ibex Peak : HD Audio controller 3.14V~3.3V~3.47V 0.006A NCP1589A
Suspend Voltage
LAN 82578DM : VDD
CLK Gen.CK505 : VDD
EC(IT8512) : VSTBY MAINON +12V power up
SPI FLASH ROM
+5V_S5 Ibex Peak : Suspend well Ref. Voltage 4.75V~5V~5.25V 0.001A
V_AXG
NCP5380
INVERTER : Vin
FAN_CPU
A GFX_VR_EN A
+3VPCU
+VCC_CORE
+5VPCU NCP5392TMNR2G
15VPCU
Quanta Computer Inc.
VIN VRON
PROJECT : ZN2
Size Document Number Rev
A
Power Map
Date: Tuesday, March 16, 2010 Sheet 3 of 49
5 4 3 2 1
5 4 3 2 1
5 4
Power Sequence S5_Power_ON
DC Jack
6
DVDD12/EVDD12
+3V_S5 MOS
G
6
+1.1V_VTT USB Port LAN
CPU VIN
DDR3
12
S
D
+1.5V_SUS RTL811DL 3
CPU_VTT_PG 3
+3VPCU
Clarkdale MAINON
D 6 11 D
+3V_S5
Lynnfield
+5V_S5
SMDDR_VTERM
LDO 12
D +3V
12
S
D
+1.8V OP
G MOS
G
S
RTC MAINON
11
H_PWRGOOD
MEM_PWRGD
RTC_RST#
3.3V Leavel NCP1587
S5_Power_ON
+VCCRTC
shift to 1.1V 5
other PCI/PCIe device 6
+5V_S5 MOS
G
1 2
+1.5V_SUS_PG
S
D
+3V_S5 3
HWPG
6 3V&5V_PCU_PG
15
PROCPWRGD
logical AND of the PCH's PWROK and SYS_PWROK
+5V_S5 +1.1V_VTT_PG +5VPCU
6 AND
+1.05V_PG
+3V
CPU_VTT_PG 3.3V Leavel 11
12 V_AXG_PG
15 Control VR delay for meet chipset spec 12
+5V
S
D
+5V
shift to 1.1V
12 MOS
G
AND
C C
+1.05V
PCH 12
MAINON
+1.8V 11
SYS_PWROK
12 PROCPWRGD
15
MEPWROK
PWROK_EC
PWROK
+1.1V_VTT
12 SYS_PWROK
MAINON MAINON
AND 11 11
VR_READY
6
ICH_SUSCLK
12
LDO MOS +1.5V_SUS
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