Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_ZQK
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5 4 3 2 1
ZQK ULV SYSTEM BLOCK DIAGRAM
Memory Down x8pcs
Channel A 128Mb X 16 * 4pcs = 1GB VRAM Max. 2G
256Mb X 16 * 4pcs = 2GB
DDR3 P21
256Mb X 16 * 8pcs
D
Ivy Bridge PCI-E GPU D
Max. 4G P13,14 IMC X8
N14P-GV2
BGA 1023
Channel B
17W Display X'TAL
27.0MHz
DDRIII-SODIMM x1pc P2,3,4,5,6
P16~P21
Dual Channel DDR III 1333/1600 MHZ
P15
FDI DMI eDP INT_eDP 4 Lane reserve
eDP Con.
DMI(x4) USB2.0-(3) Touch Panel (option)
P24
SATA 0 FDI DMI
SATA - HDD SATA
P27 Display
INT_DP
Dongle SW
Mini DP Con. P23
MINI CARD 2 SATA 1 HD3SS2521RHUR
SATA USB3.0-(3) P23
mSATA SSD P26
USB3.0-(1)
USB3.0/2.0 Port USB3.0
(Charger) USB2.0-(0) INT_HDMI
P31 Display HDMI Con. P25
C
USB2.0 Port USB2.0-(1) C
P31
PCIE-8
Panther Point PCI-E x1 MINI CARD1
USB2.0-(4) WLAN+BT
USB2.0 Port USB2.0-(10)
P31 PCH P26
BGA 989
I/O board CCD(Camera) USB2.0-(8) USB2.0
USB2.0 P7, 8, 9, 10, 11, 12 PCI-E x1 PCIE-3 RTL8411AAR RJ45 CONN
P24 Giga LAN P28
W/Card Reader
P28
X'TAL Card Reader CONN
32.768KHz
P29
X'TAL
25MHz
P8 BATTERY RTC
Azalia IHDA SPI SPI ROM*2
LPC 2M+4M(EC) P8
B B
ALC3225
AUDIO CODEC EC ITE 8587 TPM
P30
P34 P27
Int. DMIC Combo Jack ALC1001
P30 P30
AMP P30 K/B Conn Touch Pad BQ24737RGRR TPS51216RUKR Discharger
Con. P30 Batery Charger P35 +1.5V_SUS P37 Thermal Protection
P30
P41
TPL@ Touch panel TPS51225RUKR TPS51463
3V/5V P36 VCCSA P39
TPM@ TPM module HALL SENSOR Fan*2 (PWM Type)
NP@ Normal panel(Default) Speaker P32
P30
AH9249NTR-G1 TPS51650RSLR uP1642PQAG
CH@ Charge function(Default) +VCC_CORE/+VCC_GFX P40 +VGPU_CORE P43
P24
NCH@ No Charge function
TPS51219RTER TPS51211DSCR
A
EV@ Optimize SKU +1.05V_VTT +1.5V_GFX/1.05V_GFX/3V_GFX
A
P38 P42
RAMID@ RAMID strap pin
SUG@ LAN Surge
NSW@ w/o Dongle switch
SW@ w Dongle switch
Quanta Computer Inc.
KBL@ KB Backlight LED
PROJECT : ZQK
RD@ mSATA Re-driver Size Document Number Rev
1A
Block Diagram
Date: Monday, January 07, 2013 Sheet 1 of 46
5 4 3 2 1
5 4 3 2 1
Ivy Bridge Processor (DMI,PEG,FDI) (CPU)
U47A
PEG_ICOMPI and RCOMPO signals
should be shorted and routed with
- max length = 500 mils
02
- typical impedance = 43 mohms
G3 PEG_COMP PEG_ICOMPO 12mil PEG_ICOMPO signals should be routed with
PEG_ICOMPI G1
M2 PEG_ICOMPO G4 PEG_ICOMPI, PEG_RCOMPO 4mil, - max length = 500 mils
[7] DMI_TXN0 DMI_RX#[0] PEG_RCOMPO - typical impedance = 14.5 mohms
[7] DMI_TXN1 P6
P1 DMI_RX#[1]
[7] DMI_TXN2 DMI_RX#[2]
[7] DMI_TXN3
P10 H22
D DMI_RX#[3] PEG_RX#[0] J21 D
N3 PEG_RX#[1] B22
[7] DMI_TXP0 DMI_RX[0] PEG_RX#[2]
[7] DMI_TXP1 P7 D21
DMI_RX[1] PEG_RX#[3]
DMI
[7] DMI_TXP2 P3 A19
P11 DMI_RX[2] PEG_RX#[4] D17
[7] DMI_TXP3 DMI_RX[3] PEG_RX#[5] B14
K1 PEG_RX#[6] D13
[7] DMI_RXN0 DMI_TX#[0] PEG_RX#[7]
[7] DMI_RXN1 M8 A11 PEG_RX#15 [16]
N4 DMI_TX#[1] PEG_RX#[8] B10
[7] DMI_RXN2 DMI_TX#[2] PEG_RX#[9] PEG_RX#14 [16]
[7] DMI_RXN3 R2 G8 PEG_RX#13 [16]
DMI_TX#[3] PEG_RX#[10] A8
PEG_RX#[11] PEG_RX#12 [16]
[7] DMI_RXP0 K3 B6 PEG_RX#11 [16]
M7 DMI_TX[0] PEG_RX#[12] H8
[7] DMI_RXP1 DMI_TX[1] PEG_RX#[13] PEG_RX#10 [16]
[7] DMI_RXP2
P4 E5 PEG_RX#9 [16]
T3 DMI_TX[2] PEG_RX#[14] K7
[7] DMI_RXP3 DMI_TX[3] PEG_RX#[15] PEG_RX#8 [16]
K22
PEG_RX[0] K19
PEG_RX[1] C21
U7 PEG_RX[2] D19
[7] FDI_TXN0 FDI0_TX#[0] PEG_RX[3]
[7] FDI_TXN1 W 11 C19
W1 FDI0_TX#[1] PEG_RX[4] D16
[7] FDI_TXN2 FDI0_TX#[2] PEG_RX[5]
PCI EXPRESS -- GRAPHICS
[7] FDI_TXN3 AA6 C13
W6 FDI0_TX#[3] PEG_RX[6] D12
[7] FDI_TXN4 FDI1_TX#[0] PEG_RX[7]
[7] FDI_TXN5
V4 C11 PEG_RX15 [16]
Y2 FDI1_TX#[1] PEG_RX[8] C9
[7] FDI_TXN6 FDI1_TX#[2] PEG_RX[9] PEG_RX14 [16]
Intel(R) FDI
[7] FDI_TXN7 AC9 F8 PEG_RX13 [16]
FDI1_TX#[3] PEG_RX[10] C8
PEG_RX[11] PEG_RX12 [16]
C5 PEG_RX11 [16]
U6 PEG_RX[12] H6
C [7] FDI_TXP0 PEG_RX10 [16] C
W 10 FDI0_TX[0] PEG_RX[13] F6
[7] FDI_TXP1 FDI0_TX[1] PEG_RX[14] PEG_RX9 [16]
[7] FDI_TXP2 W3 K6 PEG_RX8 [16]
AA7 FDI0_TX[2] PEG_RX[15]
[7] FDI_TXP3 FDI0_TX[3]
[7] FDI_TXP4
W7 G22
T4 FDI1_TX[0] PEG_TX#[0] C23
[7] FDI_TXP5 FDI1_TX[1] PEG_TX#[1]
[7] FDI_TXP6 AA3 D23
AC8 FDI1_TX[2] PEG_TX#[2] F21
[7] FDI_TXP7 FDI1_TX[3] PEG_TX#[3] H19
AA11 PEG_TX#[4] C17
[7] FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5]
[7] FDI_FSYNC1
AC12 K15
FDI1_FSYNC PEG_TX#[6] F17
U11 PEG_TX#[7] F14
[7] FDI_INT FDI_INT PEG_TX#[8] PEG_TX#15 [16]
A15 PEG_TX#14 [16]
AA10 PEG_TX#[9] J14
[7] FDI_LSYNC0 FDI0_LSYNC PEG_TX#[10] PEG_TX#13 [16]
[7] FDI_LSYNC1 AG8 H13 PEG_TX#12 [16]
FDI1_LSYNC PEG_TX#[11] M10
PEG_TX#[12] PEG_TX#11 [16]
F10 PEG_TX#10 [16]
PEG_TX#[13] D9
PEG_TX#[14] PEG_TX#9 [16]
J4 PEG_TX#8 [16]
AF3 PEG_TX#[15]
eDP_ICOMPO 12mil EDP_COMP AD2 eDP_COMPIO F22
eDP_COMPIO 4mil INT_EDP_HPD# AG11 eDP_ICOMPO PEG_TX[0] A23
eDP_HPD PEG_TX[1] D24
PEG_TX[2] E21
EDP_AUXN AG4 PEG_TX[3] G19
[24] EDP_AUXN eDP_AUX# PEG_TX[4]
EDP_AUXP AF4 B18
[24] EDP_AUXP eDP_AUX PEG_TX[5] K17
PEG_TX[6]
DP
G17
EDP_TXN0 AC3 PEG_TX[7] E14
B [24] EDP_TXN0 eDP_TX#[0] PEG_TX[8] PEG_TX15 [16] B
EDP_TXN1 AC4 C15 PEG_TX14 [16]
[24] EDP_TXN1 eDP_TX#[1] PEG_TX[9]
EDP_TXN2 AE11 K13 PEG_TX13 [16]
[24] EDP_TXN2 eDP_TX#[2] PEG_TX[10]
EDP_TXN3 AE7 G13 PEG_TX12 [16]
[24] EDP_TXN3 eDP_TX#[3] PEG_TX[11] K10 PEG_TX11 [16]
EDP_TXP0 AC1 PEG_TX[12] G10
[24] EDP_TXP0 eDP_TX[0] PEG_TX[13] PEG_TX10 [16]
EDP_TXP1 AA4 D8 PEG_TX9 [16]
[24] EDP_TXP1 eDP_TX[1] PEG_TX[14]
EDP_TXP2 AE10 K4 PEG_TX8 [16]
[24] EDP_TXP2 eDP_TX[2] PEG_TX[15]
EDP_TXP3 AE6
[24] EDP_TXP3 eDP_TX[3]
0.22uF AC coupling Caps for PCIE GEN1/2/3
Ivy Bridge
DG 1.0 :
DP_COMPIO and ICOMPO signals The recommended AC cap value is changed to 220nF for compatibility with
should be shorted near balls and routed with PCIe Gen3 on future platforms.
- typical impedance < 25 mohms For Gen2 only designs, it is acceptable to continue to use the 100nF capacitor.
+1.05V_VTT
eDP Hot-plug (Disable)
DP & PEG Compensation HPD PU/PD resistor values based
CAD Note: Place PU resistor R327
on CRB and different to DG 1K/J_4
within 2 inches of CPU +1.05V_VTT
INT_EDP_HPD#
A A
3
EDP_COMP R669 24.9/F_4
2 EDP_HPD [24]
+1.05V_VTT Q23
2N7002K
Quanta Computer Inc.
R310
1
PEG_COMP R675 24.9/F_4 PROJECT : ZQK
100K/J_4
Size Document Number Rev
1A
Ivy Bridge 1/5 (HOST & PCIE)
Date: Monday, January 07, 2013 Sheet 2 of 46
5 4 3 2 1
5 4 3 2 1
Boot S3 S3 RSM
+1.5V_CPU
DRAM_PWRGD
03
Ivy Bridge Processor (CLK,MISC,JTAG) (CPU) 100 ns after +1.5V_CPU
SYS_PWROK reaches 80%
U47B SM_DRAMPWROK
D D
J3
BCLK CLK_CPU_BCLKP [9]
H2
BCLK# CLK_CPU_BCLKN [9]
CLOCKS
MISC
F49
[8] H_SNB_IVB# PROC_SELECT# AG3 CLK_DPLL_SSCLKP_R If motherboard only supports external graphics or if it supports
R677 0/J_4 CLK_DPLL_SSCLKP [9]
DPLL_REF_CLK AG1 CLK_DPLL_SSCLKN_R R676 0/J_4 Processor Graphics but without eDP:
DPLL_REF_CLK# CLK_DPLL_SSCLKN [9] Connect DPLL_REF_SSCLK on Processor to GND through 1K +/-
C57 5% resistor.
TP46 PROC_DETECT#
Connect DPLL_REF_SSCLK# on Processor to VCCP through 1K +/- 5% resistor
N59 CLK_PCIE_XDPP_R R750 *0/J_4
BCLK_ITP CLK_PCIE_XDPP [9]
N58 CLK_PCIE_XDPN_R R749 *0/J_4
BCLK_ITP# CLK_PCIE_XDPN [9]
TP_CATERR# C49
TP54 CATERR#
THERMAL
Isolate Space:20mils Momory Down Layout notes
A48 AT30 CAD NOTE: All DDR_COMP signals
[10,34] EC_PECI PECI SM_DRAMRST# CPU_DRAMRST# [4]
should be routed such that :-
BF44 SM_RCOMP_0 R707 140/F_4 - max length = 500 mils
R715 56/J_4 H_PROCHOT#_R C45 SM_RCOMP[0] BE43 SM_RCOMP_1 R702 25.5/F_4 - trace width = 15mils and
[34,35,40] H_PROCHOT#
DDR3
MISC
PROCHOT# SM_RCOMP[1]
SM_RCOMP[2]
BG43 SM_RCOMP_2 R705 200/F_4 - MB trace impedance < 68 mohms
C770 2 1 *43P/50V_4 (worst case resistance)
SM_RCOMP Impedance 85ohm
D45
[10] PM_THRMTRIP# THERMTRIP#
Over 130 degree C will drive low N53 XDP_PRDY#
PRDY# TP50 Layout Notes: Place near to XDP connector
N55 XDP_PREQ#
C PREQ# TP42 C
05/15PCH_XDP_TDO_VT already pull high
L56 +3V_S5 on PCH side
TCK XDP_TCLK_VT [8]
L55
TMS XDP_TMS_VT [8]
PWR MANAGEMENT
J58 XDP_TRST#
TRST# TP73 R754 51/J_4 PCH_XDP_TDO_VT
JTAG & BPM
+1.05V_VTT
R720 0/J_4 PM_SYNC_R C48 M60 XDP_TDI_VT
[7] PM_SYNC PM_SYNC TDI TP76
L59
TDO PCH_XDP_TDO_VT [8]
C774 39P/50V_4
Option for Prochot# function +1.05V_VTT
R719 0/J_4 H_PWRGOOD_R B46
[10] H_PWRGOOD UNCOREPW RGOOD K58 68 ohm for unused, 62 ohm for used
XDP_DBRST#_R R745 0/J_4
DBR# XDP_DBRST# [7]
R717 10K/J_4
H_PROCHOT# R722 62/J_4
PM_DRAM_PWRGD_R BE45 G58
Isolate Space:20mils SM_DRAMPW ROK BPM#[0] E55
TP44
BPM#[1] TP49 XDP_TMS_VT R379 51/J_4
E59
BPM#[2] TP47 XDP_TDI_VT R755 51/J_4
R735 75/F_4 G55
+1.05V_VTT BPM#[3] TP43
G59
BPM#[4] TP74
CPU_PLTRST# R740 43/J_4 CPU_PLTRST#_R D44 H60 XDP_PREQ# R378 *51/J_4
RESET# BPM#[5] TP77
J59
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