Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_ZRA
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PCB STACK UP ZRA SYSTEM DIAGRAM
LAYER 1 : TOP DDR3 channel A
DDR3-SODIMM1
LAYER 2 : GND AMD Champlain CPU THERMAL From SB
PAGE 7 SENSOR Option 14.318MHz
LAYER 3 : IN1 35mm X 35mm
A LAYER 4 : IN2 S1G4 Processor PAGE 6
A
DDR3-SODIMM2 DDR3 channel B
LAYER 5 : VCC
638P (PGA)45W/35W
LAYER 6 : IN3 CPU_CLK CLOCK GEN
PAGE 8 PAGE 4,5,6
LAYER 7 : GND ICS9LPRS476AKLFT-->HP
NBGFX_CLK
LAYER 8 : BOT SLG8SP628VTR-->HP
NBGPP_CLK
RTM880N-796 -->HP
SBLINK_CLK PAGE 3
HT3
800MHz
ATI VGA
PCI-E Madison LP VRAM DDR3 Madison /Park
PCI-Express 16X
128-bit M2 Pkg 64MX16X8,128bit
29mm X 29mm
X1 Port 0 X1 Port 2 NORTH BRIDGE PAGE 18,19,20,21,22,23 128MX16X8,128 bit
PAGE 24,25
LAN Mini PCI-E
Card
RS880
BCM 57760 DVI LVDS CRT
PCIE-LAN A12 LVDS
(Wireless LAN) LVDS On board LVDS
B 21mm X 21mm, 528pin BGA CRT B
(10/100/1000)
MUXs CRT
CRT 1 to 2 Switch On board CRT
PAGE 27 PAGE 28 (S.G)
PAGE 9,10,11,12 DVI
1 to 2 Switch
CRT connector
Lan_PCIE1 Lan_PCIE2 ALINK X4
DVI connector
USB2.0 x 1 Docking
USB connector x 3
Docking RJ45 Lan_PCIE1
SOUTH BRIDGE MIC to Docking
RJ45 connector
AMD CPU CORE (ISL6265) PAGE 27 USB2.0 Finger print MIC
PAGE 39 PAGE 32 Line out to Docking
SATA0 150MB SB820
SATA - HDD1 Line out
21mm X 21mm, 528pin BGA USB2.0 BT Line in from Docking
NB_CORE (UP6111AQDD) PAGE 29
4.5W(Ext) PAGE 32 PAGE 36 Line in
PAGE 41
C SATA1 150MB 4.3W(Int) USB2.0 C
SATA - CD-ROM
+VGPU_CORE (MAX8792ETD) PAGE 29 PAGE 13,14,15,16,17
PAGE 43 USB2.0 Ports Webcam WLAN conn
CardReader
X1 PAGE 32 PAGE 26 PAGE 28
AU6437
1.1V (UP6111AQDD)
PAGE 31
PAGE 40 LPC Azalia
TPM PAGE 28 USB BOARD
1.8V/GPU_Power/+2.5V MIC to Docking MDC USB2.0 Ports x3
Winbond KBC Codec
PAGE 44 PAGE 32
CX20672-11Z Line out to Docking
NPCE781L PAGE 30
DDR 1.5V(RT8207) PAGE 30 Line in from Docking Power BOARD
PAGE 35 PAGE 33
PAGE 42
SYSTEM 5V/3V (RT8206)
D
PAGE 38 D
1V/CPU_VDDR/Discharage SPI Digital MIC AUDIO CONN Speaker
PAGE 45 PAGE 34 CPU FAN (Phone/ MIC)
Keyboard
Touch Pad PAGE 32 PAGE 34 PAGE 35 PAGE 30 PAGE 30 PAGE 30 Quanta Computer Inc.
Charger (ISL88731) PROJECT : ZRA
PAGE 37 Size Document Number Rev
1A
Block Diagram
Date: Monday, March 29, 2010 Sheet 1 of 48
1 2 3 4 5 6 7 8
5 4 3 2 1
Danube Power On Sequence Power on sequence required:
SB800:
From VBAT VCCRTC 1.+3.3V_S5 ramp before +1.1_S5
VIN_SRC 2.+3.3V ramp before +1.8V
From AC,BATT 3.+1.8V ramp before +1.1V
+5VPCU,+3VPCU 4.+3.3V ramp before +1.1V
From Button NBSWON# 5.+3.3V_S5 ramping down time>300us
D 6.All power rails rise time >= 50us, except +3.3V_S5<=40ms D
VIN EC setting: 5ms 7.100us<=+3.3V_S5 rise time<=40ms
From EC S5_ON 9.VBAT (VCCRTC) must ramp at least 5 seconds before the S5 rails
to allow start time for the internal RTC
UP6111A +5V_S5,+3V_S5,+1.1V_S5
UP6111A HWPG_1.1V EC setting: 30ms
From EC to SB EC_RSMRST# EC setting: 100ms (only in SB820M NB_PWRGD signal)
From EC to SB DNBSWON# 40ms <= SB PWRGOOD to NB_PWRGD delay <= 42ms
From SB to EC SUSB#, SUSC# EC setting: 10ms RS880:
From EC SUSON VTERM only will be shut down in S3 mode, 1.0<(+3.3V)-(+1.8V)<2.1
2.+1.8V ramp before +1.1V
+0.75V_DDR_VTT, +SMDDR_VREF and VTERM for DDR3 SODIMM only
3.+1.1V ramp before CPU_VDDNB_CORE
+1.5VSUS
HWPG_1.5V EC setting: 10ms
From EC MAINON
GROUP A
+5V, +3V, +1.8V, +1.5V
HWPG_1.8V
BOM naming rule
C
Items Function Name Description C
+1.1V EC setting: 10ms
VRON 1 Internal CLK GEN SGN@
Actv' by +3V +2.5V 2 External CLK GEN GN@
HWPG_2.5V
3 iGPU IV@
+VCORE
CPU_VDDNB_CORE 4 dGPU SW@
GROUP B
CPU_COREPG 5 iGPU & dGPU notice SP@
CPU_VDDR
HWPG_0.9V EC setting: 10ms
+NB_CORE_ON RC=~22ms, NB_CORE should not ramp before 1.1V
SB SMBUS Table
NB_CORE CLK GEN RAM Mini Card (WLAN)
HWPG_0.95V (SB_DA0)/(SB_CL0) (+3V) V V V
SB_PWRGD_IN rise time<50ms
SB_PWRGD_IN SB_PWRGD to NB_PWRGD:40~42ms Power Plane +3V +3V +3V
B
NB_PWRGD_IN B
MOS CKT (Level shift) X X X*
Notice:
1.CPU_LDT_RST# msut be asserted a minimum of 1ms prior to the assertion of CPU_PWRGD *Reserve: There is not SMBUS function in AVL
2.CPU_CLKP/N must be within specification a minimum of 1ms prior to the assertion of CPU_PWRGD
3.CPU_PWRGD remains deasserted at least 1ms after both CPU_CLKP/N and all voltages to the processor are within EC SMBUS Table
specification for operation
4.all NB power rails(1.8V/1.2V/1.1V) valid before NB_PWRGD at least 1ms
5.stable input clocks from CLKGEN(HT_REFCLKP/N) to NB before NB_PWRGD at least 1ms Battery CPU thermal Sensor
EC775 SDA1 / SCL1 (+3VPCU) V
EC775 SDA2 / SCL2 (+3V) V
Danube GPU Power Sequence EC775 SDA3 / SCL3 ()
Power Plane +3VPCU +3V
From SB dGPU_VRON 2ms MOS CKT (Level shift) X X
MXM_PWR_EN
+3V_D
+VGPU_CORE
PG_GPIO_EN
A A
+1V
PG_1.5V_EN
+1.5V_GPU
+1.8V_GPU
Quanta Computer Inc.
PROJECT : ZRA
Size Document Number Rev
1A
Power Sequence
Date: Monday, March 29, 2010 Sheet 2 of 48
5 4 3 2 1
5 4 3 2 1
BLM21PG221SN1D(220 100M2A)_8 W/S= 15 mil/20mil SB check list tide to CPUVDDIO (+1.5VSUS)
S1G4 +2.5V +CPUVDDA
L44 CPU CLK CPU_PWRGD 300_4 R514
2.5V@250mA CPU_LDT_RST# 300_4 R509
+1.1V [email protected] +1.1V_VLDT C781 LS0805-100M-N
4.7u/6.3V_6
C483
4.7u/6.3V_6
C459
0.22u/6.3V_4
C463
3300P/50V_4
C469
12 CLK_CPU_BCLKP_PR
CLK_CPU_BCLKP_PR
CLK_CPU_BCLKN_PR
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
300_4
*300_4
R243
R505
+1.5V
*10u/6.3V_8 12 CLK_CPU_BCLKN_PR
R486 0_6
Keep trace from resisor to CPU within 0.6"
R483 0_6 +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U30D
U30A W/S= 15 mil/20mil
P/N: DG0^8000005 CLK_CPU_BCLKP_C R516 169/F_4 CLK_CPU_BCLKN_C +CPUVDDA F8 VDDA1 VSS M11 S1G4
DG0^8000009 C450 10u/6.3V_8 +1.1V_VLDT D1 VLDT_A0 HT LINK VLDT_B0 AE2 +1.1V_VLDT 10u/6.3V_8 C449 +CPUVDDA F9 VDDA2 RSVD11 W18
C746 10u/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22u/6.3V_4 C318
D DG0^80000013 C453 0.22u/6.3V_4 +1.1V_VLDT D3
VLDT_A1 VLDT_B1
AE4 +1.1V_VLDT 180P/50V_4 C448 CLK_CPU_BCLKP_PR C780 3900P/25V_4 CLK_CPU_BCLKP_C A9 A6 CPU_SVC_R D
C314 180P/50V_4 +1.1V_VLDT VLDT_A2 VLDT_B2 +1.1V_VLDT CLK_CPU_BCLKN_PR C779 3900P/25V_4 CLK_CPU_BCLKN_C CLKIN_H SVC CPU_SVD_R
DG0^80000014 D4 VLDT_A3 VLDT_B3 AE5 A8 CLKIN_L SVD A4
HT_CADINP0 E3 AD1 HT_CADOUTP0 +1.5VSUS CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 12 CPU_LDT_RST# RESET_L
HT_CADINN0 E2 AC1 HT_CADOUTN0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 12 CPU_PWRGD PWROK
HT_CADINP1 E1 AC2 HT_CADOUTP1 R490 R488 R487 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 10,12 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
SI Change from AMD request HT_CADINN1 F1 AC3 HT_CADOUTN1 B-TEST 0205 1K_4 1K_4 1K_4 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_CADINP2 L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUTP2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 AB1 AA8
HT_CADINN2 L0_CADIN_H2 L0_CADOUT_H2 HT_CADOUTN2 SIC MEMHOT_L
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 5 SIC AF4 SIC
HT_CADINP[15..0] HT_CADINP3 G1 AA2 HT_CADOUTP3 SID AF5
8 HT_CADINP[15..0] L0_CADIN_H3 L0_CADOUT_H3 5 SID SID
HT_CADINN3 H1 AA3 HT_CADOUTN3 ALERT_L AE6 W7
HT_CADINN[15..0] L0_CADIN_L3 L0_CADOUT_L3 5 ALERT_L ALERT_L THERMDC H_THRMDC 5
HT_CADINP4 J1 W2 HT_CADOUTP4 W8
8 HT_CADINN[15..0] L0_CADIN_H4 L0_CADOUT_H4 THERMDA H_THRMDA 5
HT_CADINN4 K1 W3 HT_CADOUTN4 SideBand Temp sense I2C R220 44.2/F_4 CPU_HTREF0 R6
HT_CLKINP[1..0] HT_CADINP5 L0_CADIN_L4 L0_CADOUT_L4 HT_CADOUTP5 R218 44.2/F_4 CPU_HTREF1 HT_REF0
8 HT_CLKINP[1..0] L3 L0_CADIN_H5 L0_CADOUT_H5 V1 S1G4 +1.1V_VLDT P6 HT_REF1
HT_CADINN5 L2 U1 HT_CADOUTN5 place them to CPU within 1.5"
HT_CLKINN[1..0] HT_CADINP6 L0_CADIN_L5 L0_CADOUT_L5 HT_CADOUTP6 VDDIO_FB_H
L1 U2 38 CPU_VDD0_FB_H F6 W9 VDDIO_FB_H 41
8 HT_CLKINN[1..0] HT_CADINN6 L0_CADIN_H6 L0_CADOUT_H6 HT_CADOUTN6 VDD0_FB_H VDDIO_FB_H VDDIO_FB_L
M1 L0_CADIN_L6 L0_CADOUT_L6 U3 38 CPU_VDD0_FB_L E6 VDD0_FB_L VDDIO_FB_L Y9 VDDIO_FB_L 41
HT_CTLINP[1..0] HT_CADINP7 N3 T1 HT_CADOUTP7
8 HT_CTLINP[1..0] HT_CADINN7 L0_CADIN_H7 L0_CADOUT_H7 HT_CADOUTN7
N2 R1 38 CPU_VDD1_FB_H Y6 H6 CPU_VDDNB_FB_H 38
HT_CTLINN[1..0] HT_CADINP8 L0_CADIN_L7 L0_CADOUT_L7 HT_CADOUTP8 VDD1_FB_H VDDNB_FB_H
8 HT_CTLINN[1..0] E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 38 CPU_VDD1_FB_L AB6 VDD1_FB_L VDDNB_FB_L G6 CPU_VDDNB_FB_L 38
HT_CADINN8 F5 AD3 HT_CADOUTN8
HT_CADOUTP[15..0] HT_CADINP9 L0_CADIN_L8 L0_CADOUT_L8 HT_CADOUTP9 CPU_DBRDY
8 HT_CADOUTP[15..0] F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY
HT_CADINN9 F4 AC5 HT_CADOUTN9 CPU_TMS AA9 E10 CPU_DBREQ# R520 300_4 +1.5VSUS
HT_CADOUTN[15..0] HT_CADINP10 L0_CADIN_L9 L0_CADOUT_L9 HT_CADOUTP10 CPU_TCK TMS DBREQ_L
G5 AB4 AC9
8 HT_CADOUTN[15..0] HT_CADINN10 L0_CADIN_H10 L0_CADOUT_H10 HT_CADOUTN10 CPU_TRST# TCK
H5 AB3 AD9 AE9 CPU_TDO
HT_CLKOUTP[1..0] HT_CADINP11 L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUTP11 CPU_TDI TRST_L TDO
H3 AB5 AF9
8 HT_CLKOUTP[1..0] HT_CADINN11 L0_CADIN_H11 L0_CADOUT_H11 HT_CADOUTN11 TDI
H4 AA5
HT_CLKOUTN[1..0] HT_CADINP12 L0_CADIN_L11 L0_CADOUT_L11 HT_CADOUTP12 CPUTEST23
K3 Y5 AD7 J7
8 HT_CLKOUTN[1..0] HT_CADINN12 L0_CADIN_H12 L0_CADOUT_H12 HT_CADOUTN12 TEST23 TEST28_H
K4 W5 H8
HT_CTLOUTP[1..0] HT_CADINP13 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUTP13 CPUTEST18 TEST28_L
L5 V4 H10
C 8 HT_CTLOUTP[1..0] HT_CADINN13 L0_CADIN_H13 L0_CADOUT_H13 HT_CADOUTN13 CPUTEST19 TEST18 CPUTEST17 C
M5 L0_CADIN_L13 L0_CADOUT_L13 V3 G9 TEST19 TEST17 D7 T30
HT_CTLOUTN[1..0] HT_CADINP14 M3 V5 HT_CADOUTP14 E7 CPUTEST16
8 HT_CTLOUTN[1..0] L0_CADIN_H14 L0_CADOUT_H14 TEST16 T29
HT_CADINN14 M4 U5 HT_CADOUTN14 +1.5VSUS R519 510_4 CPUTEST25H E9 F7 CPUTEST15
L0_CADIN_L14 L0_CADOUT_L14 TEST25_H TEST15 T28
HT_CADINP15 N5 T4 HT_CADOUTP15 R518 510_4 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T33
HT_CADINN15 P5 T3 HT_CADOUTN15 place them to CPU within 1.5"
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 TEST21 TEST7 C3
HT_CLKINP0 J3 Y1 HT_CLKOUTP0 CPUTEST20 AF7 K8
HT_CLKINN0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CLKOUTN0 CPUTEST24 TEST20 TEST10
J2 W1 AE7
HT_CLKINP1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUTP1 CPUTEST22 TEST24
J5 Y4 AE8 C4
HT_CLKINN1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CLKOUTN1 CPUTEST12 TEST22 TEST8
K5 Y3 AC8
L0_CLKIN_L1 L0_CLKOUT_L1 R477 1K_4 CPUTEST27 TEST12
+1.5VSUS AF8
HT_CTLINP0 HT_CTLOUTP0 TEST27 CPUTEST29H
N1 R2 C9 T72
HT_CTLINN0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CTLOUTN0 R478 *300_4 R503 *short_4 TEST9 TEST29_H
P1 R3 C2 C8
HT_CTLINP1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CTLOUTP1 TEST9 TEST29_L
P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 AA6 TEST6
HT_CTLINN1 P4 R5 HT_CTLOUTN1 R511
L0_CTLIN_L1 L0_CTLOUT_L1
A3 H18 80.6/F_4
RSVD1 RSVD10
FOX PZ63826-284R-41F A5
RSVD2 RSVD9
H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 CPUTEST29L
RSVD3 RSVD8 T73
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