Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta Quanta_ZW9
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ZW9 BLOCK DIAGRAM SVID: 152D
SSID: 6601
CPU VR
PG 36
CENTRINO (BANIAS/ DORTHAN + ODEM + ICH4-m)
POWER +1.8V VCC_CORE
A
+1.8V 2.5VSUS +3V
Port Replicator
A
3V_591 5VPCU BANIAS DC Jack
PG 33,34,35 Clocking
478 Pins Ethernet port (RJ45)
CK408 Audio Jack (Line out)
AC/BATT (Micro-FCPGA) CPU Thermal Sensor ICS950810 Serial port (COM.)
CONNECTOR PG 37 MAX6648
Parpller port (LPT.)
+VCCP PG 3,4 PG 3
PG 2 PS/2 (Mouse & Keyboard)
BATT CRT port (VGA)
CHARGER PG 37 PSB USB port
4X100MHZ
+2.5V TV out PG 31
+1.25V +2.5VSUS +1.2V +VCCP PG 23
Video
DDR SDRAM 2.5V, 266/333MHz ODEM (B1) AGP 1.5V, 66MHz +1.5V Controller LVDS LCD Panel
DDR-SODIMM1
MCH-M PG 24
+2.5VSUS +1.5V ATI M10
B
PG 8 B
+1.8V R.G,B CRT port
593 BGA PG 20,21,22
DDR-SODIMM2 PG 23
DDR 32MB/64MB
+1.8V PG 5,6,7
Primary IDE - HDD +5V
66(266)MHZ, 1.8V
PG 9
HUB I/F
+5V ATA 66/100 +VCCP +1.8V +1.5V 33MHZ, 3.3V PCI
Secondary IDE - MEDIA Bay +3V
(CDROM,DVD,CD-RW,DVD-RW) ICH4-M
PG 12 +3VSUS 421 BGA +3V +3VAUX +5V +3V
USB 2.0 USB PORT 0,1
PG 9,10,11 +5VSUS PG 13 CARDBUS & IEEE-1394 LAN 10/100/1G MINI-PCI
C AC-LINK TI PCI4510 BCM4401/5702 C
USB PORT 2,3 +3VAUX
+3V_S5
+5VSUS PG 13 IDSEL= AD22 IDSEL= AD18 IDSEL= AD20
-INTB/ -INTC (-INTA) -INTD -INTE
+3VAUX +5VA +3V -REQ2/-GNT2 -REQ0/-GNT0 -REQ1/-GNT1
CARD READER PG 14, 15 PG 17 PG 19
RJ11 USB PORT 4
MDC AUDIO PG 13
PG 18 PG 19 +12V CARD
PG 25,26,27 PORR REPLICATOR RJ45
(USB PORT 5) +5V BUS
PG 31 SLOTS
3.3V LPC, 33MHz +3V PG 18
PG 16
+3V 3V_591 +5V OTHER PCB P/N & DESCRIPTION
SIO PC87391 PC87591 FAN 1 DAZW1LYB4B9 PCB(LED/B) ZW1L YB(4L,130.28*26.29,REVB)
PG 30 DAZG1SCD8B6 PCB (CDROM/B) ZG1S(8L,11.5*94.8*1.2,REVB
100 Pins TQFP 176 Pins LQFP
DAZW1LTB4E1 PCB(TOUCHPAD) ZW1L TB(4L,109.5*44.,REVE)
D D
PG 28 PG 29 DA0ZW9AB6C0 PCB(MS/B) ZW9 AB(6L,46*69.5,REVC)
M/B PCB P/N: PROJECT : ZW9
+3/5V +5V +5V +5V +5V 3V_591
DA0ZW9MB8A9 PCB ZW9 MB(8L,334*285,REVA)
FIR RS232 Parallel DA0ZW9MB8B7 PCB ZW9 MB(8L,334*285,REVB) Quanta Computer Inc.
Touchpad Keyboard FLASH
PG 28 PG 31 PG 28 DA0ZW9MB8C5 PCB ZW9 MB(8L,334*285,REVC) Size Document Number R ev
PG 29 PG 29 PG 29 Custom 2A
FIR: BOM DEL; PAD KEEP Schematic Block Digram
Date: Friday, December 26, 2003 Sheet 1 of 39
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
S2 S1 S0 CPU 3V66[0..4] 3V66_5/66IN
1 0 0 66 66IN 66 Input
1 0 1 100 66IN 66 Input
1 1 0 200 66IN 66 Input
1 1 1 133 66IN 66 Input
0 0 0 66 66 66 M
0 0 1 100 66 66 M 20mils
A A
0 1 0 200 66 66 M L49 FBM2125HM330
VDDA_CKG
+3V
0 1 1 133 66 66 M
3 0 0 o h ms @ 1 0 0 Mh z
R188 49.9/F R373 10_0402 14M_SIO
+3V 14M_SIO (28)
C708 C705 R187 49.9/F
C715 .01U_0402 10U/10V/U R372 10_0402 14M_ICH
+3V_S5 14M_ICH (10)
*12P_0402 R190 49.9/F
XIN R189 49.9/F R437 10_0402 CLK14_AUDIO
CLK14_AUDIO (25)
2
R369 R365 R359 49.9/F
*1K_0402 1K_0402 Y4 R358 49.9/F
26
27
C735 R380 14.318MHz/18PF U28
SELPSB1_CLK *.1U_0402 C714 *2M 2 56 14M_REF
VDDA
VSSA
1
*12P_0402 XTAL_IN REF
SELPSB0_CLK XOUT 3 45 R_HCLK_MCH R351 33_0402 HCLK_MCH
XTAL_OUT CPU2 HCLK_MCH (5)
5
44 R_HCLK_MCH# R350 33_0402 HCLK_MCH#
CPU#2 HCLK_MCH# (5)
(10) SUSA# 2
4 25 49 R_HCLK_CPU R353 33_0402 HCLK_CPU
PWR_DWN# CPU1 HCLK_CPU (3)
R368 R364 1 34 48 R_HCLK_CPU# R352 33_0402 HCLK_CPU#
(10,29) SUSB# (10) STP_PCI# PCI_STP# CPU#1 HCLK_CPU# (3)
1K_0402 *1K_0402 53
(10,36) STP_CPU# CPU_STP#
U31 52 R_HCLK_ITP R363 33_0402
HCLK_ITP (3)
3 *7SH08 CK_PGD# CPU0 R_HCLK_ITP# R362 33_0402
28 PWRGD# CPU#0 51 HCLK_ITP# (3)
f r o m IMV P 4 CGCLK_SMB 30 CK-408 33
R499 0 CGDAT_SMB SCLK 3V66_0
29 SDATA 3V66_1/VCH 35
R360 1K_0402
SELPSB2_CLK 40 24
B SELPSB1_CLK SEL2 66IN/3V66_5 R_CLK66_ICH R381 33_0402 CLK66_ICH B
55 SEL1 66B2/3V66_4 23 CLK66_ICH (10)
SELPSB0_CLK 54 22 R_CLK66_MCH R382 33_0402 CLK66_MCH
SEL0 66B1/3V66_3 CLK66_MCH (6)
L47 21 R_CLK66_AGP R383 33_0402 CLK66_AGP
CLKVDD_CPU 30mils 1
66B0/3V66_2 CLK66_AGP (20)
+3V VDD_REF
FBM2125HM330 8 7 R _PCLK_ICH R390 33_0402 P CLK_ICH
VDD_PCI_1 PCI_F2 PCLK_ICH (9)
14 VDD_PCI_2 PCI_F1 6
C695 C700 C687 C710 C706 C709 C690 C688 19 5
10U/10V/U .1U_0402 .1U_0402 .1U_0402 .1U_0402 .1U_0402 .1U_0402 .1U_0402 VDD_3V66_1 PCI_F0
32 VDD_3V66_2
18 R_PCLK_SIO R384 33_0402 PCLK_SIO
PCI6 PCLK_SIO (28)
46 17 R_PCLK_PCM R385 33_0402 PCLK_PCM
VDD_CPU_1 PCI5 PCLK_PCM (14)
50 VDD_CPU_2 PCI4 16
13 R_PCLK_591 R386 33_0402 PCLK_591
PCI3 PCLK_591 (29)
12 R_PCLK_MINI R387 33_0402 PCLK_MINI
PCI2 PCLK_MINI (19)
R349 475/F IR EF 42 11 R_PCLK_LAN R388 33_0402 PCLK_LAN
IREF PCI1 PCLK_LAN (17)
10 R_PCLK_1394 R389 33_0402
R361 CK_MULT0 PCI0
+3V 43 MULT0 R_CLK48_USB R356 33_0402 CLK48_USB
L45 FBM2125HM330 10K_0402 20mils 48M_USB
48M_DOT
39
38
CLK48_USB (10)
CLK_48MVDD 37
+3V VDD_48MHZ
GND_3V66_1
GND_3V66_2
+3V
GND_PCI_1
GND_PCI_2
GND_IREF
GND_CPU
GND_REF
3 0 0 o h ms @ 1 0 0 Mh z Combin C.B. and IEEE1394.
C691 C689 ZW9 used TI PCI54510.
10U/10V/U .1U_0402 So, remove this CLK trace,
These are for backdrive issue Z0301
36 GND_48MHZ
L44
R354 R355 BK1608HM121 CK-TITAN-B
4
9
15
20
31
41
47
*10K_0402 *10K_0402
2
Q39
*RHU002N06 C LKGND R186 0_0805
C CGDAT_SMB C
(8,10) PDAT_SMB 3 1
CYPRESS: CY28346 R193 0_0805
ICS: ICS950810
R375 0_0805
R500 0
R357 0_0805
+3V
2
Q35
*RHU002N06
3 1 CGCLK_SMB
(8,10) PCLK_SMB
CLK14_AUDIO
R501 0
14M_ICH
THOSE ARE RESERVE FOR EMI 14M_SIO
R73
CK_PGD#
+3V
CLK66_ICH P CLK_ICH C696 C694 C767
10K_0402 CLK66_MCH PCLK_SIO *10P_0402 *10P_0402 *10P_0402
CLK66_AGP PCLK_591
3
3
R393 R531 CLK48_USB PCLK_MINI
D 2 2 PCLK_LAN D
VCC_CORE IMVP_PWG (10,36)
Q55 PCLK_1394
220 Q40 *10K_0402 L23 PCLK_PCM
1
1
3904 *15nF
*RHU002N06
C720 C723 C721 C725
Z0302 *10P_0402 *10P_0402 *10P_0402 *10P_0402 PROJECT : ZW9
C718 C716 C724 C722 C719
C306 C717 *10P_0402 *10P_0402 *10P_0402 *10P_0402
*10P_0402 *10P_0402 *10P_0402 Quanta Computer Inc.
Size Document Number R ev
A3 1B
CLOCK GENERATOR
Date: Friday, December 26, 2003 Sheet 2 of 39
1 2 3 4 5 6 7 8
A B C D E
HD#[0..63]
HD#[0..63] (5)
U3A
HA #[3..31]
(5) HA#[3..31]
HA#3 P4 A19 H D#0
HA#4 A3# D0# H D#1
U4 A25
HA#5
HA#6
V3
A4#
A5#
Banias D1#
D2# A22 H D#2
H D#3
R3 A6# D3# B21
HA#7 V2 A24 H D#4
HA#8 A7# D4# H D#5
HA#9
W1
T4
A8# 1 OF 3 D5# B26
A21 H D#6
HA#10 A9# D6# H D#7
4 W2 A10# D7# B20 4
HA#11 Y4 C20 H D#8
HA#12 A11# D8# H D#9
Y1 A12# D9# B24
HA#13 U1 D24 HD#10
HA#14 A13# D10# HD#11
AA3 A14# D11# E24
HA#15 Y3 C26 HD#12
HA#16 A15# D12# HD#13
AA2 A16# D13# B23
HA#17 AF4 E23 HD#14
HA#18 A17# D14# HD#15
AC4 A18# D15# C25
HA#19 AC7 H23 HD#16
HA#20 A19# D16# HD#17
AC3 A20# D17# G25
HA#21 AD3 L23 HD#18
HA#22 A21# D18# HD#19
AE4 A22# D19# M26
HA#23 AD2 H24 HD#20
HA#24 A23# D20# HD#21
AB4 A24# D21# F25
HA#25 AC6 REQUEST DATA G24 HD#22
HA#26 A25# D22# HD#23
AD5 PHASE PHASE J23
HA#27 A26# D23# HD#24 +3V +3V
AE2 SIGNALS SIGNALS M23
HA#28 A27# D24# HD#25
AD6 A28# D25# J25
2
HA#29 AF3 L26 HD#26 R25 100 280VCC
HA#30 A29# D26# HD#27
AE1 A30# D27# N24
HA#31 AF1 M25 HD#28 3 1 THCLK_SMB
A31# D28# (29,37) MBCLK
H26 HD#29 C39
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