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5 4 3 2 1
ZHN SHB ULT SYSTEM BLOCK DIAGRAM 01
Memory Down Dual Channel DDR3L
Channel A 1Rx16 1600 MHZ SMBUS
D D
IMC Haswell ULT 15W
P14 eDP
eDP EDP Conn.
MCP 1168pins
Channel B 1Rx16 USB2-2
CCD(Camera) PWR GATED
DC+GT3
P15
40 mm X 24 mm P16
SATA0
NGFF SATA SATA
P20 PWR GATED DDI1
DDI HDMI Conn. P18
USB3-1 USB3 Port
USB2-1 MB side
PWR GATED P10
Daughter Board
USB3.0/2.0 PWR GATED
USB2-6 USB2-0 LTE
C
I/O Board Conn. Mini Card C
Integrated PCH
P21
USB2.0
Cardreader PCIECLOCK-0 SIM card
GL823 CLK
PCI-E x1 PCIE-1
USB2-4
MINI CARD
USB2 Port USB2-3 WLAN+BT
DB side
PWR GATED X'TAL PWR GATED P19
32.768KHz
P28
X'TAL 24MHz
ALS
ISL29023
P28
I2C1
I2C
TOUCH
B
SCREEN B
Google Debug conn I2C0
P28
TRACKPAD
Azalia P2~P13 PWR GATED
IHDA P25
SPI
LPC SPI ROM
W25Q64FVSSIG P8
BQ24707A TPS51216
Batery Charger P29 PP1350 P30
TPS51225 TPS54318
Int. MIC ALC283 TI TM4E1G31H6ZRBI SLB9655TT1.2 FW4.32 PP3300_DSW/PP5000 P34 PP1500_PCH_TS P33
AMIC
AUDIO CODEC EC TPM P22
P23 P23 PWR GATED P26 TPS51622 Thermal Protection
+VCCIN P32 Discharger P33
A
X'TAL TPS51211 A
32.768KHz PP1050_PCH_SUS
P31
Thermal IC Quanta Computer Inc.
Combo HP Speaker P28
Fan Driver HALL
K/B Con. (PWM Type) SENSOR P27
P25 P25
PROJECT : ZHN
Size Document Number Rev
3B
Block Diagram
Date: Monday, August 26, 2013 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
Haswell ULT (DISPLAY,eDP)
U24A HSW_ULT_DDR3L
02
eDP Panel
[18] INT_HDMITX2N C54 C45 EDP_TXN0 EDP_TXN0 [16]
C55 DDI1_TXN0 EDP_TXN0 B46 EDP_TXP0
D [18] INT_HDMITX2P EDP_TXP0 [16] D
B58 DDI1_TXP0 EDP_TXP0 A47
HDMI
[18] INT_HDMITX1N DDI1_TXN1 EDP_TXN1
[18] INT_HDMITX1P C58 B47
B55 DDI1_TXP1 EDP_TXP1
[18] INT_HDMITX0N DDI1_TXN2
[18] INT_HDMITX0P A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
[18] INT_HDMICLK- DDI1_TXN3 EDP_TXP2
[18] INT_HDMICLK+ B57 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
C51 EDP_TXP3
C50 DDI2_TXN0 A45 EDP_AUXN
DDI2_TXP0 EDP_AUXN EDP_AUXN [16]
C53 B45 EDP_AUXP
DP
DDI2_TXN1 EDP_AUXP EDP_AUXP [16]
B54
C49 DDI2_TXP1 D20 EDP_RCOMP R25 24.9/F_4
DDI2_TXN2 EDP_RCOMP +VCCIOA_OUT
B50 A43 DP_UTIL R343 *0_4 PCH_BL_PWM
A53 DDI2_TXP2 EDP_DISP_UTIL
B53 DDI2_TXN3
DDI2_TXP3
eDP_RCOMP
R356 *0_4
Trace length < 100 mils
Trace width = 20 mils
1 OF 19 DP_UTIL [16] Trace spacing = 25 mils
C C
HSW_ULT_DDR3L
U24I
[16,26] PCH_BL_PWM PCH_BL_PWM B8 B9 HDMI_DDCCLK_SW [18]
PCH_BL_EN A9 EDP_BKLCTL DDPB_CTRLCLK C9
[16,26] PCH_BL_EN EDP_BKLEN DDPB_CTRLDATA HDMI_DDCDATA_SW [18] PP3300_PCH
[16,26] PCH_EDP_VDD_EN PCH_EDP_VDD_EN C6 eDP SIDEBAND D9
EDP_VDDEN DDPC_CTRLCLK D11
DDPC_CTRLDATA
PCH_GPIO77 R30 10K_4
PCH_GPIO77 U6 +3V PCH_GPIO78 R391 10K_4
PCH_GPIO78 P4 PIRQA/GPIO77 C5 PCH_GPIO79 R27 10K_4
PIRQB/GPIO78 +3V DDPB_AUXN
PCH_GPIO79 N4 +3V B6 PCH_GPIO80 R383 10K_4
PCH_GPIO80 N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5 SIM_DET R376 10K_4
PIRQD/GPIO80 +3V DDPB_AUXP
PCI_PME# AD4 +3V_S5 A6 TOUCH_INT_L_DX R378 10K_4
TP97 PME PCIE DDPC_AUXP ALS_INT_L R24 10K_4
U7 +3V TRACKPAD_INT_DX R385 10K_4
SIM_DET L1 GPIO55
[21] SIM_DET GPIO52 +3V
TOUCH_INT_L_DX L3 +3V C8 INT_HDMI_HPD [18]
[16] TOUCH_INT_L_DX GPIO54 DDPB_HPD
ALS_INT_L R5 +3V A8
[28] ALS_INT_L GPIO51 DDPC_HPD
TRACKPAD_INT_DX L4 +3V D6
[25] TRACKPAD_INT_DX GPIO53 EDP_HPD EDP_HPD [16]
B B
R342
9 OF 19 100K_4 DDPB/C_CTRLDATA has an iPD 20K,
When PU at rising edge of
Haswell C-1 2c BGA 1.6GHz ULV 15W 2+2 i5-4200U QS for proto/AJ0QEVEVT01 PCH_PWROK, the DDI port will
be detected
A A
Quanta Computer Inc.
PROJECT :ZHN
Size Document Number Rev
3B
Haswell 1/5 (DDI/eDP)
Date: Monday, August 26, 2013 Sheet 2 of 39
5 4 3 2 1
5 4 3 2 1
Haswell ULT
U24C HSW_ULT_DDR3L
(DDR3L)
U24D
Haswell Processor (DDR3L)
HSW_ULT_DDR3L
03
[14] M_A_DQ<0> AH63 AU37 M_A_DIM0_CK_DDR0_DN [14]
AH62 SA_DQ0 SA_CLK#0 AV37 AY31 AM38
[14] M_A_DQ<1> SA_DQ1 SA_CLK0 M_A_DIM0_CK_DDR0_DP [14] [15] M_B_DQ<0> SB_DQ0 SB_CK#0 M_B_DIM0_CK_DDR0_DN [15]
[14] M_A_DQ<2> AK63 AW36 [15] M_B_DQ<1> AW31 AN38 M_B_DIM0_CK_DDR0_DP [15]
AK62 SA_DQ2 SA_CLK#1 AY36 AY29 SB_DQ1 SB_CK0 AK38
[14] M_A_DQ<3> SA_DQ3 SA_CLK1
6/25 Add TP127~TP132 for XDP by Intel. [15] M_B_DQ<2> SB_DQ2 SB_CK#1
[14] M_A_DQ<4> AH61 [15] M_B_DQ<3> AW29 AL38
AH60 SA_DQ4 AU43 AV31 SB_DQ3 SB_CK1
D
[14] M_A_DQ<5> SA_DQ5 SA_CKE0 M_A_DIM0_CKE0 [14] [15] M_B_DQ<4> SB_DQ4 D
[14] M_A_DQ<6> AK61 AW43 [15] M_B_DQ<5> AU31 AY49 M_B_DIM0_CKE0 [15]
SA_DQ6 SA_CKE1 TP127 SB_DQ5 SB_CKE0
[14] M_A_DQ<7> AK60 AY42 [15] M_B_DQ<6> AV29 AU50
SA_DQ7 SA_CKE2 TP128 SB_DQ6 SB_CKE1 TP130
[14] M_A_DQ<8> AM63 AY43 [15] M_B_DQ<7> AU29 AW49
SA_DQ8 SA_CKE3 TP129 SB_DQ7 SB_CKE2 TP131
[14] M_A_DQ<9> AM62 [15] M_B_DQ<8> AY27 AV50
SA_DQ9 SB_DQ8 SB_CKE3 TP132
[14] M_A_DQ<10> AP63 AP33 M_A_DIM0_CS0_N [14] [15] M_B_DQ<9> AW27
AP62 SA_DQ10 SA_CS#0 AR32 AY25 SB_DQ9 AM32
[14] M_A_DQ<11> SA_DQ11 SA_CS#1 TP41 [15] M_B_DQ<10> SB_DQ10 SB_CS#0 M_B_DIM0_CS0_N [15]
[14] M_A_DQ<12> AM61 [15] M_B_DQ<11> AW25 AK32
SA_DQ12 SB_DQ11 SB_CS#1 TP35
[14] M_A_DQ<13> AM60 AP32 [15] M_B_DQ<12> AV27
SA_DQ13 SA_ODT0 TP40 SB_DQ12
[14] M_A_DQ<14> AP61 [15] M_B_DQ<13> AU27 AL32
SA_DQ14 SB_DQ13 SB_ODT0 TP31
[14] M_A_DQ<15> AP60 AY34 M_A_RAS_N [14] [15] M_B_DQ<14> AV25
AP58 SA_DQ15 SA_RAS AW34 AU25 SB_DQ14 AM35
[14] M_A_DQ<16> SA_DQ16 SA_WE M_A_WE_N [14] [15] M_B_DQ<15> SB_DQ15 SB_RAS M_B_RAS_N [15]
[14] M_A_DQ<17> AR58 AU34 M_A_CAS_N [14] [15] M_B_DQ<16> AM29 AK35 M_B_WE_N [15]
AM57 SA_DQ17 SA_CAS AK29 SB_DQ16 SB_WE AM33
[14] M_A_DQ<18> SA_DQ18 [15] M_B_DQ<17> SB_DQ17 SB_CAS M_B_CAS_N [15]
[14] M_A_DQ<19> AK57 AU35 M_A_BS0 [14] [15] M_B_DQ<18> AL28
AL58 SA_DQ19 SA_BA0 AV35 AK28 SB_DQ18 AL35
[14] M_A_DQ<20> SA_DQ20 SA_BA1 M_A_BS1 [14] [15] M_B_DQ<19> SB_DQ19 SB_BA0 M_B_BS0 [15]
[14] M_A_DQ<21> AK58 AY41 M_A_BS2 [14] [15] M_B_DQ<20> AR29 AM36 M_B_BS1 [15]
AR57 SA_DQ21 SA_BA2 AN29 SB_DQ20 SB_BA1 AU49
[14] M_A_DQ<22> SA_DQ22 [15] M_B_DQ<21> SB_DQ21 SB_BA2 M_B_BS2 [15]
[14] M_A_DQ<23> AN57 AU36 M_A_A<0> [14] [15] M_B_DQ<22> AR28
AP55 SA_DQ23 SA_MA0 AY37 AP28 SB_DQ22 AP40
[14] M_A_DQ<24> SA_DQ24 SA_MA1 M_A_A<1> [14] [15] M_B_DQ<23> SB_DQ23 SB_MA0 M_B_A<0> [15]
[14] M_A_DQ<25> AR55 AR38 M_A_A<2> [14] [15] M_B_DQ<24> AN26 AR40 M_B_A<1> [15]
AM54 SA_DQ25 SA_MA2 AP36 AR26 SB_DQ24 SB_MA1 AP42
[14] M_A_DQ<26> SA_DQ26 SA_MA3 M_A_A<3> [14] [15] M_B_DQ<25> SB_DQ25 SB_MA2 M_B_A<2> [15]
[14] M_A_DQ<27> AK54 AU39 M_A_A<4> [14] [15] M_B_DQ<26> AR25 AR42 M_B_A<3> [15]
AL55 SA_DQ27 SA_MA4 AR36 AP25 SB_DQ26 SB_MA3 AR45
[14] M_A_DQ<28> SA_DQ28 SA_MA5 M_A_A<5> [14] [15] M_B_DQ<27> SB_DQ27 SB_MA4 M_B_A<4> [15]
[14] M_A_DQ<29> AK55 AV40 M_A_A<6> [14] [15] M_B_DQ<28> AK26 AP45 M_B_A<5> [15]
AR54 SA_DQ29 SA_MA6 AW39 AM26 SB_DQ28 SB_MA5 AW46
[14] M_A_DQ<30> SA_DQ30 SA_MA7 M_A_A<7> [14] [15] M_B_DQ<29> SB_DQ29 SB_MA6 M_B_A<6> [15]
[14] M_A_DQ<31> AN54 DDR CHANNEL A AY39 M_A_A<8> [14] [15] M_B_DQ<30> AK25 AY46 M_B_A<7> [15]
AY58 SA_DQ31 SA_MA8 AU40 AL25 SB_DQ30 SB_MA7 AY47
[14] M_A_DQ<32> SA_DQ32 SA_MA9 M_A_A<9> [14] [15] M_B_DQ<31> SB_DQ31 SB_MA8 M_B_A<8> [15]
[14] M_A_DQ<33> AW58 AP35 M_A_A<10> [14] [15] M_B_DQ<32> AY23 DDR CHANNEL B AU46 M_B_A<9> [15]
AY56 SA_DQ33 SA_MA10 AW41 AW23 SB_DQ32 SB_MA9 AK36
[14] M_A_DQ<34> SA_DQ34 SA_MA11 M_A_A<11> [14] [15] M_B_DQ<33> SB_DQ33 SB_MA10 M_B_A<10> [15]
[14] M_A_DQ<35> AW56 AU41 M_A_A<12> [14] [15] M_B_DQ<34> AY21 AV47 M_B_A<11> [15]
AV58 SA_DQ35 SA_MA12 AR35 AW21 SB_DQ34 SB_MA11 AU47
[14] M_A_DQ<36> SA_DQ36 SA_MA13 M_A_A<13> [14] [15] M_B_DQ<35> SB_DQ35 SB_MA12 M_B_A<12> [15]
[14] M_A_DQ<37> AU58 AV42 M_A_A<14> [14] [15] M_B_DQ<36> AV23 AK33 M_B_A<13> [15]
C AV56 SA_DQ37 SA_MA14 AU42 AU23 SB_DQ36 SB_MA13 AR46 C
[14] M_A_DQ<38> SA_DQ38 SA_MA15 M_A_A<15> [14] [15] M_B_DQ<37> SB_DQ37 SB_MA14 M_B_A<14> [15]
[14] M_A_DQ<39> AU56 [15] M_B_DQ<38> AV21 AP46 M_B_A<15> [15]
AY54 SA_DQ39 AJ61 AU21 SB_DQ38 SB_MA15
[14] M_A_DQ<40> SA_DQ40 SA_DQSN0 M_A_DQS_DN<0> [14] [15] M_B_DQ<39> SB_DQ39
[14] M_A_DQ<41> AW54 AN62 M_A_DQS_DN<1> [14] [15] M_B_DQ<40> AY19 AW30 M_B_DQS_DN<0> [15]
AY52 SA_DQ41 SA_DQSN1 AM58 AW19 SB_DQ40 SB_DQSN0 AV26
[14] M_A_DQ<42> SA_DQ42 SA_DQSN2 M_A_DQS_DN<2> [14] [15] M_B_DQ<41> SB_DQ41 SB_DQSN1 M_B_DQS_DN<1> [15]
[14] M_A_DQ<43> AW52 AM55 M_A_DQS_DN<3> [14] [15] M_B_DQ<42> AY17 AN28 M_B_DQS_DN<2> [15]
AV54 SA_DQ43 SA_DQSN3 AV57 AW17 SB_DQ42 SB_DQSN2 AN25
[14] M_A_DQ<44> SA_DQ44 SA_DQSN4 M_A_DQS_DN<4> [14] [15] M_B_DQ<43> SB_DQ43 SB_DQSN3 M_B_DQS_DN<3> [15]
[14] M_A_DQ<45> AU54 AV53 M_A_DQS_DN<5> [14] [15] M_B_DQ<44> AV19 AW22 M_B_DQS_DN<4> [15]
AV52 SA_DQ45 SA_DQSN5 AL43 AU19 SB_DQ44 SB_DQSN4 AV18
[14] M_A_DQ<46> SA_DQ46 SA_DQSN6 M_A_DQS_DN<6> [14] [15] M_B_DQ<45> SB_DQ45 SB_DQSN5 M_B_DQS_DN<5> [15]
[14] M_A_DQ<47> AU52 AL48 M_A_DQS_DN<7> [14] [15] M_B_DQ<46> AV17 AN21 M_B_DQS_DN<6> [15]
AK40 SA_DQ47 SA_DQSN7 AU17 SB_DQ46 SB_DQSN6 AN18
[14] M_A_DQ<48> SA_DQ48 [15] M_B_DQ<47> SB_DQ47 SB_DQSN7 M_B_DQS_DN<7> [15]
[14] M_A_DQ<49> AK42 AJ62 M_A_DQS_DP<0> [14] [15] M_B_DQ<48> AR21
AM43 SA_DQ49 SA_DQSP0 AN61 AR22 SB_DQ48 AV30
[14] M_A_DQ<50> SA_DQ50 SA_DQSP1 M_A_DQS_DP<1> [14] [15] M_B_DQ<49> SB_DQ49 SB_DQSP0 M_B_DQS_DP<0> [15]
[14] M_A_DQ<51> AM45 AN58 M_A_DQS_DP<2> [14] [15] M_B_DQ<50> AL21 AW26 M_B_DQS_DP<1> [15]
AK45 SA_DQ51 SA_DQSP2 AN55 AM22 SB_DQ50 SB_DQSP1 AM28
[14] M_A_DQ<52> SA_DQ52 SA_DQSP3 M_A_DQS_DP<3> [14] [15] M_B_DQ<51> SB_DQ51 SB_DQSP2 M_B_DQS_DP<2> [15]
[14] M_A_DQ<53> AK43 AW57 M_A_DQS_DP<4> [14] [15] M_B_DQ<52> AN22 AM25 M_B_DQS_DP<3> [15]
AM40 SA_DQ53 SA_DQSP4 AW53 AP21 SB_DQ52 SB_DQSP3 AV22
[14] M_A_DQ<54> SA_DQ54 SA_DQSP5 M_A_DQS_DP<5> [14] [15] M_B_DQ<53> SB_DQ53 SB_DQSP4 M_B_DQS_DP<4> [15]
[14] M_A_DQ<55> AM42 AL42 M_A_DQS_DP<6> [14] [15] M_B_DQ<54> AK21 AW18 M_B_DQS_DP<5> [15]
AM46 SA_DQ55 SA_DQSP6 AL49 AK22 SB_DQ54 SB_DQSP5 AM21
[14] M_A_DQ<56> SA_DQ56 SA_DQSP7 M_A_DQS_DP<7> [14] [15] M_B_DQ<55> SB_DQ55 SB_DQSP6 M_B_DQS_DP<6> [15]
[14] M_A_DQ<57> AK46 [15] M_B_DQ<56> AN20 AM18 M_B_DQS_DP<7> [15]
AM49 SA_DQ57 AP49 AR20 SB_DQ56 SB_DQSP7
[14] M_A_DQ<58> SA_DQ58 SM_VREF_CA +VREF_CA_CPU [15] M_B_DQ<57> SB_DQ57
[14] M_A_DQ<59> AK49 AR51 +VREFDQ_SA_M3 [15] M_B_DQ<58> AK18
AM48 SA_DQ59 SM_VREF_DQ0 AP51 AL18 SB_DQ58
[14] M_A_DQ<60> SA_DQ60 SM_VREF_DQ1 +VREFDQ_SB_M3 [15] M_B_DQ<59> SB_DQ59
[14] M_A_DQ<61> AK48 [15] M_B_DQ<60> AK20
AM51 SA_DQ61 AM20 SB_DQ60
[14] M_A_DQ<62> SA_DQ62 [15] M_B_DQ<61> SB_DQ61
[14] M_A_DQ<63> AK51 [15] M_B_DQ<62> AR18
SA_DQ63 AP18 SB_DQ62
[15] M_B_DQ<63> SB_DQ63
B B
3 OF 19 4 OF 19
A A
Quanta Computer Inc.
PROJECT : ZHN
Size Document Number Rev
3B
Haswell 2/5 (DDR3 I/F)
Date: Monday, August 26, 2013 Sheet 3 of 39
5 4 3 2 1
5 4 3 2 1
Haswell ULT (SIDEBAND)
04
H_PECI (50ohm)
D D
Route on microstrip only
Spacing >18 mils
Trace Length: 0.4~6.125 iches
H_PWRGOOD (50ohm)
Trace Length: 1~11.25 inches HSW_ULT_DDR3L
U24B
CPU_PLTRST# (50ohm)
Trace Length: 10~17 inches PROC_DETECT D61
TP71 PROC_DETECT
CATERR# K61 MISC
TP80 CATERR
H_PECI N62 J62 XDP_PRDY#
[26] H_PECI PECI PRDY XDP_PRDY# [13]
K62 XDP_PREQ#
PREQ XDP_PREQ# [13]
E60 XDP_TCK0 TCK,TMS
PROC_TCK XDP_TCK0 [8,13]
E61 XDP_TMS_CPU Trace Length < 9000mils
H_PROCHOT# R380 56_4 H_PROCHOT#_R K63 JTAG PROC_TMS E59 XDP_TRST# XDP_TMS_CPU [13]
[17,26,29,32] H_PROCHOT# PROCHOT PROC_TRST XDP_TRST# [8,13]
THERMAL F63 XDP_TDI_CPU
PROC_TDI F62 XDP_TDO_CPU XDP_TDI_CPU [8,13]
PROC_TDO XDP_TDO_CPU [8,13]
[26] CPU_PGOOD R360 *Short_4 H_PWRGOOD_R C61
PROCPWRGD PWR
C J60 XDP_BPM#0 C
BPM#0 XDP_BPM#0 [13]
H60 XDP_BPM#1
BPM#1 XDP_BPM#1 [13]
SM_RCOMP[0:2] H61 XDP_BPM#2 BPM#[0:7]
BPM#2 TP73
Trace length < 500 mils H62 XDP_BPM#3 Trace Length 1~6 inches
BPM#3 TP75
SM_RCOMP_0 AU60 K59 XDP_BPM#4
Trace width = 12~15 mils SM_RCOMP_1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_BPM#5
TP76 Length match < 300 mils
Trace spacing = 20 mils SM_RCOMP_2 AU61 SM_RCOMP1 BPM#5 K60 XDP_BPM#6
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