Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta quanta_fx5_0504_a00-03(1)
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1 2 3 4 5 6 7 8
POWER
SYSTEM PG 39
FX5 SAPPORO-INTEGRATED
RESET CIRCUIT
REV : A00
A A
RUN POWER SW PG 46
FAN & THERMAL
AMD S1 CLOCK EMC4001
DDR2-SODIMM1 667/800 MHZ DDR II
Turion 64 Rev.F Dual-Core/ SLG84605TTR PG 35
PG 7,8
Dual-Core 35W PG 18
BATT PG 40 DDR2-SODIMM2 667/800 MHZ DDR II (638 S1g1 socket)
CHARGER PG 7,8
PG 3,4,5,6
AC/BATT PG 41
CONNECTOR HT_LINK
DDR2-MEMORY DEVICE
400 MHZ DDR II MINI-CARD
8MX16X4 84-PIN FBGA PCIEx1
WWAN
PG 13
PG 26
CPU VR PG 44 Panel CONN. LVDS RS690T
MINI-CARD x2
B
PG 19 PCIEx2 B
WLAN & WPAN
465 FCBGA
DC/DC PG 45 TVout CONN. TVOUT PG 25
+3.3V_SUS/+5V_SUS/+15V_SUS PG 20
PCIEx1 EXPRESS-CARD
REGULATOR PG 42 CRT CONN. VGA R5538
VCC_NB & +1.2V_ALW_SUS
PG 9,10,11,12,13
PG 20 PG 27
USB2.0 (P6)
REGULATOR PG 43
+1.8V_SUS/+0.9V_DDR_VTT
USB2.0 (P4)
A_LINK
+1.5V_RUN USB2.0 (P9)
CD-ROM
IDE
USB2.0 (P7) BlueTooth
PG 24
PG 38
SATA - HDD SB600
SATA USB2.0 (P0,P1)(EXT SIDE)
External USBX4
PG 24 USB2.0 (P2,P3)(EXT BACK)
PG 28
C IHDA C
549 BGA
USB2.0 (P8) (GX2) External USB
USB2.0 (P5)
AUDIO/AMP MDC PG 28
PG 14,15,16,17 33MHz PCI
PG 33,34 PG 27 SPI
1394 BCM 4401
S/PDIF LPC
FX5 M/B PCB 8-in-1 Card Reader (B0)
R5C833
Digital MIC Camera PG 21,22,23 PG 36
SIO SIO
MEC5025
PG 34
128KB Flash BC ECE5021 USER
TMKBC INTERFACE RJ45/Magnetics
Audio Jacks SNIFFER PG 38
128 Pins VTQFP 128 Pins VTQFP PG 37
D
PG 29 PG 30 D
PG 34
SPI BC PS/2 QUANTA
FLASH Touchpad/ CIR Title
COMPUTER
Schematic Block Diagram1
Keyboard
PG 31 Size Document Number Rev
PG32 PG 32 FX5 1A
Date: Friday, May 04, 2007 Sheet 1 of 61
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
INDEX Power States
Control S3/ S4/ S5/
Pg# Description REQ# / GNT# - Power Rail S0/M0 S3/M1 S3/M1 S4/M1
PCI Device IDSEL Signal M-off M-off M-off
1 Schematic Block Diagram PIRQ (S/Y)
2 Front Page +15V_ALW
3-6 Turion 64 Cardbus (OZ601) AD17 N/A
+5V_ALW
7-8 DDRII SO-DIMMX2
A Docking AD24 N/A A
9-13 RS690T +3.3V_ALW
14-17 SB600 REQ1# / GNT#1 -
MediaCard & 1394 PIRQC# (Media Card), +1.2V_ALW_SUS
18 Clock Generator (R5C832) AD17
PIRQD# (1394) & SERIRQ.
19 LCD Conn. & CK-SSCD +5V_SUS
20 CRT&TV CONN
REQ0# / GNT#0 - +3.3V_SUS
21-23 8-IN-1 CARD READER LOM (4401) AD16 PIRQB#.
24 SATA (HDD&CD_ROM) +1.8V_SUS
25 MINI-PCI
+0.9V_DDR_VTT
26 WWAN
27 Express Card & Smart Card +5V_RUN
28 USB
+1.2V_RUN
29 SIO (MEC5025)
30 SIO (ECE5011) +1.8V_RUN
31 FLASH,RTC&KC
PCI-E Destination (S/Y) +3.3V_RUN
32 TP&CIR
B B
33 Audio CODEC(STAC9205)& +2.5V_RUN
Lane0 MINI CARD-3 WWAN
34 AUDIO CONN Digital MIC/Camera
+VCC_VCRE
35 FAN & Thermal Lane1 MINI CARD-1 WLAN
36 LAN (BCM4401) +NB_VCORE
Lane2 MINI CARD-2 WPAN
37 LAN JACK
+LCDVCC
38 SWITCH&LED Lane3 EXPRESS CARD
39 System Reset Circuit +3.3V_WLAN
40 Charger
+3.3V_LAN
41 DCIN,BATT CONNECTOR
42 +1.2V_ALW_SUS,+NB_VCORE
43 +1.8V_SUS,+0.9V_DDR_VTT,+1.5V_RUN
44 VHCORE(MAX8774)
45 +3.3V_ALW,+5V_ALW
46 RUN Power Switch
C 48 EMI CAP & SCREW HOLE PM Table C
49 SMBUS BLOCK
IC Chips USB Port# Destination (S/Y) Power +5V_RUN
50 POWER BLOCK
Plan +3.3V_RUN
51 Chipset Power Block +15V_ALW +5V_SUS
0 Right side Pair Top as viewed in the front +2.5V_RUN
+5V_ALW +3.3V_SUS +1.8V_RUN
1 Right side Pair Bot. as viewed in the front +3.3V_ALW +1.8V_SUS +1.5V_RUN
+1.2V_ALW_SUS +0.9V_DDR_VTT +1.2V_RUN
2 Rear Side Top
State +VCC_CORE
3 Rear Side Bottom +NB_CORE
4 Left side Pair Tot as viewed in the front S0 ON ON ON
SB600
5 Camera S3 ON ON OFF
6 Express Card S5 S4/AC ON OFF OFF
7 3rd Mini Card USB(WPAN) S5 S4 on battery OFF OFF OFF
D D
8 Left side Pair Bot. as viewed in the front
9 WWAN QUANTA
Title
COMPUTER
Index, DNI, Power & Ground
Size Document Number Rev
FX5 1A
Date: Friday, May 04, 2007 Sheet 2 of 61
1 2 3 4 5 6 7 8
5 4 3 2 1
LAYOUT: Place bypass cap on topside of board
PROCESSOR HYPERTRANSPORT INTERFACE NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
TO OTHER HT POWER PINS
D
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER PLACE CLOSE TO VLDT0 POWER PINS D
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+1.2V_RUN
+1.2V_RUN
U18A
D4 VLDT_A3 VLDT_B3 AE5
D3 VLDT_A2 VLDT_B2 AE4
1
1
D2 AE3 C155 C565 C566 C589 C578 C562 C572
VLDT_A1 VLDT_B1
D1 VLDT_A0 VLDT_B0 AE2
4.7U/6.3V/0603 4.7U/6.3V/0603 4.7U/6.3V/0603 0.22U/6.3V 0.22U/6.3V 180P/50V 180P/50V
2
2
9 HT_CADIN15 N5 L0_CADIN_H15 L0_CADOUT_H15 T4 HT_CADOUT15 9
9 HT_CADIN#15 P5 L0_CADIN_L15 L0_CADOUT_L15 T3 HT_CADOUT#15 9
9 HT_CADIN14 M3 L0_CADIN_H14 L0_CADOUT_H14 V5 HT_CADOUT14 9
9 HT_CADIN#14 M4 L0_CADIN_L14 L0_CADOUT_L14 U5 HT_CADOUT#14 9 X5R NPO
9 HT_CADIN13 L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CADOUT13 9
9 HT_CADIN#13 M5 L0_CADIN_L13 L0_CADOUT_L13 V3 HT_CADOUT#13 9
C 9 HT_CADIN12 K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 HT_CADOUT12 9 C
9 HT_CADIN#12 K4 L0_CADIN_L12 L0_CADOUT_L12 W5 HT_CADOUT#12 9
9 HT_CADIN11 H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 HT_CADOUT11 9
9 HT_CADIN#11 H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 HT_CADOUT#11 9
9 HT_CADIN10 G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 HT_CADOUT10 9
9 HT_CADIN#10 H5 L0_CADIN_L10 L0_CADOUT_L10 AB3 HT_CADOUT#10 9
9 HT_CADIN9 F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 HT_CADOUT9 9
9 HT_CADIN#9 F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 HT_CADOUT#9 9
9 HT_CADIN8 E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 HT_CADOUT8 9
9 HT_CADIN#8 F5 L0_CADIN_L8 L0_CADOUT_L8 AD3 HT_CADOUT#8 9
9 HT_CADIN7 N3 L0_CADIN_H7 L0_CADOUT_H7 T1 HT_CADOUT7 9
9 HT_CADIN#7 N2 L0_CADIN_L7 L0_CADOUT_L7 R1 HT_CADOUT#7 9
9 HT_CADIN6 L1 L0_CADIN_H6 L0_CADOUT_H6 U2 HT_CADOUT6 9
9 HT_CADIN#6 M1 L0_CADIN_L6 L0_CADOUT_L6 U3 HT_CADOUT#6 9
9 HT_CADIN5 L3 L0_CADIN_H5 L0_CADOUT_H5 V1 HT_CADOUT5 9
9 HT_CADIN#5 L2 L0_CADIN_L5 L0_CADOUT_L5 U1 HT_CADOUT#5 9
9 HT_CADIN4 J1 L0_CADIN_H4 L0_CADOUT_H4 W2 HT_CADOUT4 9
9 HT_CADIN#4 K1 L0_CADIN_L4 L0_CADOUT_L4 W3 HT_CADOUT#4 9
9 HT_CADIN3 G1 L0_CADIN_H3 L0_CADOUT_H3 AA2 HT_CADOUT3 9
9 HT_CADIN#3 H1 L0_CADIN_L3 L0_CADOUT_L3 AA3 HT_CADOUT#3 9
9 HT_CADIN2 G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 HT_CADOUT2 9
9 HT_CADIN#2 G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 HT_CADOUT#2 9
9 HT_CADIN1 E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 HT_CADOUT1 9
9 HT_CADIN#1 F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 HT_CADOUT#1 9
B
9 HT_CADIN0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUT0 9 B
9 HT_CADIN#0 E2 L0_CADIN_L0 L0_CADOUT_L0 AC1 HT_CADOUT#0 9
Place R167 and R166 less 9 HT_CLKIN1 J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HT_CLKOUT1 9
than 100mils from CPU 9 HT_CLKIN#1 K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CLKOUT#1 9
9 HT_CLKIN0 J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 HT_CLKOUT0 9
+1.2V_RUN J2 W1
9 HT_CLKIN#0 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUT#0 9
R167 51 HT_CTLIN1 P3 T5 HT_CTLOUT1 Place T96 and T98 less
L0_CTLIN_H1 L0_CTLOUT_H1 T96
HT_CTLIN#1 P4 R5 HT_CTLOUT#1
R166 51 L0_CTLIN_L1 L0_CTLOUT_L1 T98 than 100mils from CPU
9 HT_CTLIN0 N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CTLOUT0 9
9 HT_CTLIN#0 P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CTLOUT#0 9
Athlon 64 S1
Processor Socket
A A
QUANTA
Title
COMPUTER
ATHLON64 HT I/F
Size Document Number Rev
FX5 1A
Date: Friday, May 04, 2007 Sheet 3 of 61
5 4 3 2 1
A B C D E
+1.8V_SUS
Place Capacitors for +0.9V_CPU_M_VREF_SUS < 1" from the RS690T.
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
+0.9V_CPU_M_VREF_SUS trace length < 6", trace width > 15mils and
20mils spacing from any adjacent signals in X, Y, Z directions. Processor DDR2 Memory Interface
C700 R579
0.1U/10V 1K/F U18C
CPU_VTT_SUS_SENSE R577 DDR_B_D63 AD11 AA12 DDR_A_D63
7 DDR_B_D[0..63] MB_DATA63 MA_DATA63 DDR_A_D[0..63] 7
+0.9V_CPU_M_VREF_SUS 1 2 DDR_B_D62 AF11 AB12 DDR_A_D62
should be routed as 10mils *0_0603_NC
+V_DDR_VREF
DDR_B_D61 MB_DATA62 MA_DATA62 DDR_A_D61
AF14 MB_DATA61 MA_DATA61 AA14
4 and 10mils spacing from any DDR_B_D60 AE14 AB14 DDR_A_D60 4
MB_DATA60 MA_DATA60
adjacent signals in X, Y, Z DDR_B_D59 Y11 MB_DATA59 MA_DATA59 W11 DDR_A_D59
directions. C694 C683 R578 DDR_B_D58 AB11 Y12 DDR_A_D58
0.1U/10V 1N/50V 1K/F DDR_B_D57 MB_DATA58 MA_DATA58 DDR_A_D57
AC12 MB_DATA57 MA_DATA57 AD13
DDR_B_D56 AF13 AB13 DDR_A_D56
CPU_VTT_SUS_SENSE DDR_B_D55 MB_DATA56 MA_DATA56 DDR_A_D55
43 CPU_VTT_SUS_SENSE AF15 MB_DATA55 MA_DATA55 AD15
DDR_B_D54 AF16 AB15 DDR_A_D54
DDR_B_D53 MB_DATA54 MA_DATA54 DDR_A_D53
*470P/50V_NC
AC18 MB_DATA53 MA_DATA53 AB17
1
C647
DDR_B_D52 AF19 Y17 DDR_A_D52
+1.8V_SUS DDR_B_D51 MB_DATA52 MA_DATA52 DDR_A_D51
AD14 MB_DATA51 MA_DATA51 Y14
U18B +0.9V_DDR_VTT DDR_B_D50 AC14 W14 DDR_A_D50
2
DDR_B_D49 MB_DATA50 MA_DATA50 DDR_A_D49
AE18 MB_DATA49 MA_DATA49 W16
2
W17 D10 DDR_B_D48 AD18 AD17 DDR_A_D48
R231 MEMVREF VTT1 DDR_B_D47 MB_DATA48 MA_DATA48 DDR_A_D47
VTT2 C10 AD20 MB_DATA47 MA_DATA47 Y18
39.2/F Y10 B10 DDR_B_D46 AC20 AD19 DDR_A_D46
VTT_SENSE VTT3 DDR_B_D45 MB_DATA46 MA_DATA46 DDR_A_D45
VTT4 AD10 AF23 MB_DATA45 MA_DATA45 AD21
W10 DDR_B_D44 AF24 AB21 DDR_A_D44
1
M_ZN VTT5 DDR_B_D43 MB_DATA44 MA_DATA44 DDR_A_D43
AE10 MEMZN VTT6 AC10 AF20 MB_DATA43 MA_DATA43 AB18
M_ZP AF10 AB10 DDR_B_D42 AE20 AA18 DDR_A_D42
MEMZP VTT7 DDR_B_D41 MB_DATA42 MA_DATA42 DDR_A_D41
VTT8 AA10 AD22 MB_DATA41 MA_DATA41 AA20
2
A10 DDR_B_D40 AC22 Y20 DDR_A_D40
R235 VTT9 DDR_B_D39 MB_DATA40 MA_DATA40 DDR_A_D39
AE25 MB_DATA39 MA_DATA39 AA22
39.2/F V19 Y16 DDR_B_D38 AD26 Y22 DDR_A_D38
7,8 DDR_CS3_DIMMA# MA0_CS_L3 MA0_CLK_H2 M_CLK_DDR1 7 MB_DATA38 MA_DATA38
J22 AA16 DDR_B_D37 AA25 W21 DDR_A_D37
7,8 DDR_CS2_DIMMA# MA0_CS_L2 MA0_CLK_L2 M_CLK_DDR#1 7 MB_DATA37 MA_DATA37
V22 E16 DDR_B_D36 AA26 W22 DDR_A_D36
7,8 DDR_CS1_DIMMA# M_CLK_DDR0 7
1
MA0_CS_L1 MA0_CLK_H1 DDR_B_D35 MB_DATA36 MA_DATA36 DDR_A_D35
7,8 DDR_CS0_DIMMA# T19 MA0_CS_L0 MA0_CLK_L1 F16 M_CLK_DDR#0 7 AE24 MB_DATA35 MA_DATA35 AA21
DDR_B_D34 AD24 AB22 DDR_A_D34
DDR_B_D33 MB_DATA34 MA_DATA34 DDR_A_D33
7,8 DDR_CS3_DIMMB# Y26 MB0_CS_L3 MB0_CLK_H2 AF18 M_CLK_DDR3 7 AA23 MB_DATA33 MA_DATA33 AB24
J24 AF17 DDR_B_D32 AA24 Y24 DDR_A_D32
7,8 DDR_CS2_DIMMB# MB0_CS_L2 MB0_CLK_L2 M_CLK_DDR#3 7 MB_DATA32 MA_DATA32
W24 A17 DDR_B_D31 G24 H22 DDR_A_D31
7,8 DDR_CS1_DIMMB# MB0_CS_L1 MB0_CLK_H1 M_CLK_DDR2 7 MB_DATA31 MA_DATA31
PLACE THEM CLOSE TO U23 A18 DDR_B_D30 G23 H20 DDR_A_D30
7,8 DDR_CS0_DIMMB# MB0_CS_L0 MB0_CLK_L1 M_CLK_DDR#2 7 MB_DATA30 MA_DATA30
DDR_B_D29 D26 E22 DDR_A_D29
CPU WITHIN 1" DDR_B_D28 MB_DATA29 MA_DATA29 DDR_A_D28
7,8 DDR_CKE3_DIMMB H26 MB_CKE1 MB0_ODT1 W23 M_ODT3 7,8 C26 MB_DATA28 MA_DATA28 E21
J23 W26 DDR_B_D27 G26 J19 DDR_A_D27
7,8 DDR_CKE2_DIMMB MB_CKE0 MB0_ODT0 M_ODT2 7,8 MB_DATA27 MA_DATA27
J20 V20 DDR_B_D26 G25 H24 DDR_A_D26
3 7,8 DDR_CKE1_DIMMA MA_CKE1 MA0_ODT1 M_ODT1 7,8 MB_DATA26 MA_DATA26 3
DDR_B_D25 DDR_A_D25
To SODIMM socket A (near)
To SODIMM socket B (Far)
7,8 DDR_CKE0_DIMMA J21 MA_CKE0 MA0_ODT0 U19 M_ODT0 7,8 E24 MB_DATA25 MA_DATA25 F22
DDR_B_D24 E23 F20 DDR_A_D24
7,8 DDR_A_MA[0..15] MB_DATA24 MA_DATA24
DDR_A_MA15 K19 J25 DDR_B_MA15 DDR_B_D23 C24 C23 DDR_A_D23
MA_ADD15 MB_ADD15 DDR_B_MA[0..15] 7,8 MB_DATA23 MA_DATA23
DDR_A_MA14 K20 J26 DDR_B_MA14 DDR_B_D22 B24 B22 DDR_A_D22
DDR_A_MA13 MA_ADD14 MB_ADD14 DDR_B_MA13 DDR_B_D21 MB_DATA22 MA_DATA22 DDR_A_D21
V24 MA_ADD13 MB_ADD13 W25 C20 MB_DATA21 MA_DATA21 F18
DDR_A_MA12 K24 L23 DDR_B_MA12 DDR_B_D20 B20 E18 DDR_A_D20
DDR_A_MA11 MA_ADD12 MB_ADD12 DDR_B_MA11 DDR_B_D19 MB_DATA20 MA_DATA20 DDR_A_D19
L20 MA_ADD11 MB_ADD11 L25 C25 MB_DATA19 MA_DATA19 E20
DDR_A_MA10 R19 U25 DDR_B_MA10 DDR_B_D18 D24 D22 DDR_A_D18
DDR_A_MA9 MA_ADD10 MB_ADD10 DDR_B_MA9 DDR_B_D17 MB_DATA18 MA_DATA18 DDR_A_D17
L19 MA_ADD9 MB_ADD9 L24 A21 MB_DATA17 MA_DATA17 C19
DDR_A_MA8 L22 M26 DDR_B_MA8 DDR_B_D16 D20 G18 DDR_A_D16
DDR_A_MA7 MA_ADD8 MB_ADD8 DDR_B_MA7 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo