Service Manuals, User Guides, Schematic Diagrams or docs for : Quanta quanta_sw1
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UBM1
SW1-INTEGRATED GFX
SW1 M/B PCB
A A
RUN POWER
SYSTEM 1.8V & 0.9V PG 37 CLOCKS
SW PG 41 DC/DC
RESET CIRCUIT Yonah ICS954310
PG 41 +3VPCU
(478 Micro-FCPGA) +5VPCU
CPU VR PG 39
PG 17
PG 40
AC/BATT
CONNECTOR BATT PG 3,4
PG 36
PG 36 CHARGER
Panel Connector PG 18
533/667 MHz FSB
LVDS
533/667 MHZ DDR II
DDR2-SODIMM1
B
SDVO CH7307 DVI DVI Connector B
PG 15,16 Calistoga PG 19
PG 19
533/667 MHZ DDR II 1466 uFCBGA
DDR2-SODIMM2 VGA CRT Connector
PG 15,16 PG 20
PG 5,6,7,8,9,10 S-Video I/O Board
Connector
PG 28
DMI interface
USB2.0 (P2) (EXT Left Side)
USB
SATA - HDD SATA USB2.0 (P0,P1) (EXT Right Side)
PG 26 Port
PG 20 USB2.0 (P4)
ICH7-M Replicator
PATA
IDE
HDD/ODD 652 BGA
C PG 20 LAN 88E8036/53 RJ45/Magnetics PG 35 C
PG 34
Bluetooth USB2.0 (P5) PG 33
PG 27 33MHz PCI
PG 11,12,13,14
AC97/Azalia PCIEx2
USB2.0 (P6,P7) 1394/Card Reader MINI-PCI
LPC (Debug)
AUDIO MODEM PCI7402
PG 21,22 PG 42
PG 30,31 PG 32
KBC 1394
PC97551VPC
H/P to Audio
DOCK Jacks EXPRESS-CARD
PG 25 MINI-CARD
PG 31 PG 31
WLAN & WWAN
D D
PG 23,24
FWH PS/2
Flash Keyboard
USER Touchpad FAN & THERMAL PROJECT : SW1
S/W&Led
INTERFACE Quanta Computer Inc.
PG 25 PG 28 PG 27
PG 31 PG 29 Size Document Number Rev
CustomSchematic Block Diagram1 1A
Date: Wednesday, November 16, 2005 Sheet 1 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
INDEX
Power & Ground
Pg# Description DNI LIST
Label Pg# Description Control Signal
1 Schematic Block Diagram
DC_IN+ AC ADAPTER (20V)
2 Front Page
PBATT+ MAIN BATTERY + (10~17V)
3-4 Yonah
A A
PWR_SRC MAIN POWER (10~20V)
5-10 Calistoga
RTC_PWR3_3V RTC & PCL POWER (3_3V)
11-14 ICH7
+12V +12V DRUNPWROK
15-16 DDRII SO-DIMM(200P)
VHCORE CPU CORE POWER (1.25/1.15V) RUNPWROK
17 Clock Generator
V1_2RUN AGTL+ POWER (1.2V) RUNPWROK
18-21 VGA
22 LCD Conn. & SSP
+3VRUN SLP_S3# CTRLD POWER RUN_ON
23 CRT Conn
+3VSUS SLP_S5# CTRLD POWER SUS_ON
24 SATA & IDE Conn
+5VALW 8051 POWER (5V)
25 PCCARD/Conn & 1394
+5VRUN SLP_S3# CTRLD POWER RUN_ON
26 Express Card & Smart Card
B B
+5VSUS SLP_S5# CTRLD POWER SUS_ON
27 Mini Card
+5VHDD HDD POWER (5V) HDDC_EN#
28 MDC Conn.
+5VMOD MODULE POWER (5V) MODC_EN#
29 SIO (MEC5004)
STRB#/5V EXTERNAL FDD POWER (5V) FDD/LPT#
30 SIO (MEC5018)
+5VFAN1, +5VFAN2 FAN POWER (5V) FAN_OFF/ON#
31 SERIAL PORT & USB
VDDA AUDIO ANALOG POWER (5V) RUN_ON
32 Flash ROM
1_8VSUS RESUME WELL IN ICH
33 TP,BT & FIR
1_8VRUN SLP_S3# CTRLD POWER
34 Switch,Keyboard & LED
+3VALW 8051 POWER (3V)
35 FAN & Thermal
V1_5RUN AGP I/O POWER
C 36-37 Audio CODEC(STAC9200)/Phone Jack C
38-39 LOM (BCM5752)/Switch
GND ALL PAGES DIGITAL GROUND
40-41 Docking Conn/Q-Switch
42 System Reset Circuit
43-44 Battery Selector & Charger GNDP CPU POWER GND
45 DDR2_1.8VSUS, 0.9V
CGNDP CHARGER GND
46 1.5VSUS,1.05V(VTT)
47 CPU Power DGNDP DC/DC POWER GND
48 D/D Power LANGND COMBO CONN GND
49 RUN Power Switch
D 50 VGA DC/DC D
51 DCIN/Batt Conn.
52 PAD& SCREW PROJECT : SW1
53 SMBUS BlOCK Quanta Computer Inc.
Size Document Number Rev
CustomIndex, DNI, Power & Ground 1A
Date: Wednesday, November 16, 2005 Sheet 2 of 46
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
H_A#[3..16] U32A
5 H_A#[3..16]
H_A#3 J4 H1
A[3]# ADS# H_ADS# 5 H_D#[0..63] U32B H_D#[0..63]
H_A#4 L4 E2 +1.05V_VCCP
A[4]# BNR# H_BNR# 5 5 H_D#[0..63] H_D#[0..63] 5
H_A#5 M3 G5 H_D#0 E22 AA23 H_D#32
A[5]# BPRI# H_BPRI# 5 D[0]# D[32]#
H_A#6 K5 H_D#1 F24 AB24 H_D#33
A[6]# D[1]# D[33]#
2
H_A#7 M1 H5 H_D#2 E26 V24 H_D#34
A[7]# DEFER# H_DEFER# 5 D[2]# D[34]#
ADDR GROUP 0
ADDR GROUP 0
H_A#8 N2 F21 R35 H_D#3 H22 V26 H_D#35
A[8]# DRDY# H_DRDY# 5 D[3]# D[35]#
DATA GRP 0
H_A#9 1K/F H_D#4 H_D#36
DATA GRP 2
J1 A[9]# DBSY# E1 H_DBSY# 5 F23 D[4]# D[36]# W25
CONTROL
H_A#10 N3 H_D#5 G25 U23 H_D#37
H_A#11 A[10]# H_D#6 D[5]# D[37]# H_D#38
P5 F1 H_BR0# 5 E25 U25
1
A
H_A#12 A[11]# BR0# V_CPU_GTLREF H_D#7 D[6]# D[38]# H_D#39 A
P2 A[12]# E23 D[7]# D[39]# U22
H_A#13 L1 D20 H_IERR# H_D#8 K24 AB25 H_D#40
A[13]# IERR# D[8]# D[40]#
2
H_A#14 P4 B3 H_D#9 G24 W22 H_D#41
A[14]# INIT# H_INIT# 11 D[9]# D[41]#
H_A#15 P1 Place voltage H_D#10 J24 Y23 H_D#42
H_A#16 A[15]# R34 H_D#11 D[10 D[42]# H_D#43
R1 A[16]# LOCK# H4 H_LOCK# 5 divider within J23 D[11]# D[43]# AA26
L2 2K/F H_D#12 H26 Y26 H_D#44
5 H_ADSTB#0 H_REQ#[0..4] ADSTB[0]# 0.5" of GTLREF D[12]# D[44]#
B1 H_RESET# H_D#13 F26 Y22 H_D#45
5 H_REQ#[0..4] H_RESET# 5
1
H_REQ#0 K3 RESET# pin H_D#14 D[13]# D[45]# H_D#46
REQ[0]# RS[0]# F3 H_RS#0 5 K22 D[14]# D[46]# AC26
H_REQ#1 H2 F4 H_D#15 H25 AA24 H_D#47
REQ[1]# RS[1]# H_RS#1 5 D[15]# D[47]#
H_REQ#2 K2 G3 H23 W24
REQ[2]# RS[2]# H_RS#2 5 5 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 5
H_REQ#3 J3 G2 G22 Y25
REQ[3]# TRDY# H_TRDY# 5 5 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 5
H_REQ#4 L5 J26 V23
H_A#[17..31] REQ[4]# 5 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 5
5 H_A#[17..31] HIT# G6 H_HIT# 5
H_A#17 Y2 E4 H_D#[0..63] H_D#[0..63]
A[17]# HITM# H_HITM# 5 5 H_D#[0..63] H_D#[0..63] 5
H_A#18 U5 H_D#16 N22 AC22 H_D#48
H_A#19 A[18]# ITP_BPM#0 H_D#17 D[16]# D[48]# H_D#49
R3 A[19]# BPM[0]# AD4 T106 K25 D[17]# D[49]# AC23
H_A#20 W6 AD3 ITP_BPM#1 H_D#18 P26 AB22 H_D#50
A[20]# BPM[1]# T138 D[18]# D[50]#
XDP/ITP SIGNALS
H_A#21 U4 AD1 ITP_BPM#2 H_D#19 R23 AA21 H_D#51
A[21]# BPM[2]# T139 D[19]# D[51]#
DATA GRP 1
H_A#22 ITP_BPM#3 H_D#20 H_D#52
DATA GRP 3
Y5 A[22]# BPM[3]# AC4 T140 L25 D[20]# D[52]# AB21
H_A#23 U2 AC2 ITP_BPM#4 H_D#21 L22 AC25 H_D#53
A[23]# PRDY# T141 D[21]# D[53]#
H_A#24 R4 AC1 ITP_BPM#5 C445 H_D#22 L23 AD20 H_D#54
H_A#25 A[24]# PREQ# ITP_TCK H_THERMDA H_THERMDC H_D#23 D[22]# D[54]# H_D#55
T5 A[25]# TCK AC5 1 2 M23 D[23]# D[55]# AE22
H_A#26 T3 AA6 ITP_TDI H_D#24 P25 AF23 H_D#56
H_A#27 A[26]# TDI ITP_TDO *2200P_50V_NC H_D#25 D[24]# D[56]# H_D#57
W3 A[27]# TDO AB3 P22 D[25]# D[57]# AD24
H_A#28 W5 AB5 ITP_TMS H_D#26 P23 AE21 H_D#58
H_A#29 A[28]# TMS ITP_TRST# H_D#27 D[26]# D[58]# H_D#59
Y4 A[29]# TRST# AB6 T24 D[27]# D[59]# AD21
H_A#30 W2 C20 ITP_DBRESET# H_D#28 R24 AE25 H_D#60
A[30]# DBR# ITP_DBRESET# 13 D[28]# D[60]#
H_A#31 Y1 H_D#29 L26 AF25 H_D#61
A[31]# H_PROCHOT# H_D#30 D[29]# D[61]# H_D#62
5 H_ADSTB#1 V4 ADSTB[1]# PROCHOT D21 H_PROCHOT# H_THERMDA,H_THERMDC T25 D[30]# D[62]# AF22
B A24 H_THERMDA routing together. H_D#31 N24 AF26 H_D#63 B
THERMDA H_THERMDA 29 D[31]# D[63]#
THERM
A6 A25 H_THERMDC M24 AD23
11 H_A20M# A20M# THERMDC H_THERMDC 29 Trace width/Spacing 5 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 5
11 H_FERR# A5 FERR# 5 H_DSTBP#1 N25 DSTBP[1]# DSTBP[3]# AE24 H_DSTBP#3 5
11 H_IGNNE# C4 IGNNE# THERMTRIP# C7 =10/10 mil 5 H_DINV#1 M26 DINV[1]# DINV[3]# AC20 H_DINV#3 5
D5 PM_THRMTRIP# V_CPU_GTLREF AD26 R26 COMP0
11 H_STPCLK# STPCLK# PM_THRMTRIP# 6 GTLREF COMP[0]
C6 MISC U26 COMP1
H CLK
11 H_INTR LINT0 COMP[1]
B4 A22 U1 COMP2
11 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 17 COMP[2]
A3 A21 Populate R401 for R402 1 2 *51_NC C26 V1 COMP3
11 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 17 TEST1 COMP[3]
Yonah B0 and R401 1
AA1 RSVD[01]# 2 51 D25 TEST2 DPRSTP# E5 H_DPRSTP#
H_DPRSTP# 11,39
AA4 T22
forward. B5 H_DPSLP#
RSVD[02]# RSVD[12]# DPSLP# H_DPSLP# 11
+1.05V_VCCP AB2 D24
RSVD[03]# DPWR# H_DPWR# 5
RESERVED
AA3 RSVD[04]# 6,17 CPU_MCH_BSEL0 B22 BSEL[0] PWRGOOD D6 H_PWRGOOD 11
M4 RSVD[05]# RSVD[13]# D2 6,17 CPU_MCH_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 5,11
N5 RSVD[06]# RSVD[14]# F6 6,17 CPU_MCH_BSEL2 C21 BSEL[2] PSI# AE6 H_PSI# 39
1
T2 D3 +1.05V_VCCP
RSVD[07]# RSVD[15]# Yonah
V3 RSVD[08]# RSVD[16]# C1
R50 B2 AF1 R51 56
75 RSVD[09]# RSVD[17]# H_IERR#
C3 RSVD[10]# RSVD[18]# D22 1 2 CPU_BSEL BSEL2 BSEL1 BSEL0
C23 R400 56
2
RSVD[19]# PM_THRMTRIP# 1
B25 RSVD[11]# RSVD[20]# C24 2 133 0 0 1
Yonah 166 0 1 1 R399 *56_NC
H_PROCHOT# H_DPRSTP# 1 2
+1.05V_VCCP
R398 *56_NC
H_DPSLP# 1 2
3V_S5
C C
+1.05V_VCCP Place R4,R361 & R7 close to CPU. R397
*1K_NC Populate R398,R399 for Yonah A0,
+1.05V_VCCP de-pop R398,R399 for Yonah A1
R396
10K
1
1
1
1
1
2
R13 R14 R19 R37 R33 R395 0
54.9/F *51_NC 39.2/F 150 *54.9/F_NC PM_THRMTRIP# 1 3 THERM_CPUDIE_L# COMP0
THERM_CPUDIE# 25
COMP1
Q26 COMP2
2
2
2
2
2
H_RESET# *MMBT3904_NC +1.05V_VCCP COMP3
ITP_TDO
ITP_TMS R15 *150_NC
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