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service manual
DTT1609
CONTENTS
1 MAIN BOARD TROUBLE SHOOTING GUIDE
1.1 SHORT TEST
1.2 POWER
1.3 MAIN CLOCK
1.4 CVBS
1.5 RGB
1.6 AUDIO
# ADDITIONAL TROUBLESOOTHING
2 SCHEMATIC.COMPONENT LAYOUT AND BOM OF POWER SUPPLY
2.1 SCHEMATIC OF POWER SUPPLY
2.2 COMPONENT LAYOUT OF POWER SUPPLY
3 SCHEMATIC.COMPONENT LAYOUT AND BOM OF MAIN BOARD
3.1 SCHEMATIC OF MAIN BOARD
3.2 COMPONENT LAYOUT OF MAIN BOARD
3.3 BOM OF MAIN BOARD
Main Board
8
6
7
4
2
3 5
1
9 10
Main Board Trouble Shooting Guide
(DTT1609)
Here are the procedures you can refer to whenever terrestrial receivers do not
operate properly. You can check problems and repair the units on the basic level
according to the following procedures
1. SHORT TEST
Before turning on AC power, check POSITIVE VOLTAGE and also check whether SHORT
between GROUND's and PIN SHORT for TUNER are detected or not.
1
2. Checking POWER.
+12V(SCART),+5V(ANTENNA_POWER,IR,VIDEO BUFFER,HDMI,USB), +3.3V(TUNER, FLASH,
CPU),+2.5V(DEMOD),+1.5V(DDR3,CPU),+1.3V(CPU DEMOD)
1
+5V
+12V
6
+5V For HDMI
+3V3 For
Tuner
2
+3V3
10
+3V3
For Cpu
2
+1V3 For
+1V5 Cpu
For Cpu
3
+1V5 For
DDR3
+2V5 For
10
DEMOD
5
+1V3 For
DEMOD
8
+5V For
USB
+5V For Video
Buffer
+5V For Audio
3. Check MAIN CLOCK 24MHz and SYSTEM CLOCK (PLL) to operate normally after SYSTEM
operates.
For the first thing, check 24MHz from Y401 flows into [OSCI(PIN B18)] of MAIN
CPU
If the 24MHz is unstable, Check Y401 is damaged or not.
If you are firm belief of damage for the device, then replace the device.
And then, check that 800MHz is being supplied to DDR3 with RESET
If the clock 800MHz on Pin-J7&K7 of U401 is not generated from inside of the
chip,Please check the soldering state of U401,U402 and U403
(MAIN CLOCK) 24MHz
(DDR3 CLOCK) 800MHz
MAIN CLOCK
DDR3 CLOCK 800Mhz
4. In case that MAIN CPU operates normally but there is no VIDEO display.
In case of no OSD display.
If OSD is not displayed, check first if VIDEO SIGNAL is detected from
[R419(CVBS),R416(R),R417(G),R418(B)] of MAIN CPU.
And then, check any part with no DATA after checking VIDEO SIGNAL from VIDEO
SIGNAL PORT of MAIN CPU, or SCART
In case of no MPEG display
There can be a variety of reasons for the case
Check first that CHANNEL of TP SIGNAL is locked properly.
After this signal input to the resistor connected to MAIN CPU is done normally,
A/V DATA comes out from MAIN CPU and flows into MPEG CHIP(MAIN CPU). If there is no
problem to here, it is thought that MAIN CPU and channel are operating without any
fault.
In case of no MPEG display to this point, inspect any disorder by checking
U701(TUNER IC) and I/F of MAIN CPU.
VIDEO SIGNAL
If wave-form is not like this
picture, check that wave-form
output is normal from each
terminal
5. In case of no MPEG and no OSD at the same time.
Check that 1Vp_p(0.7Vp_p for RGB) comes out normally from VIDEO PART(CVBS) of
MAIN CPU.
RED GREEN BLUE CVBS
7. In case of normal VIDEO SIGNAL flowing out but abnormal AUDIO SIGNAL.
Check that ADAC_L(U201 PIN2),ADAC_R(U201 PIN9) signals have normal inputting and
outputting from MAIN CPU. The signal is linked to SCART.
# ADDITIONAL TROUBLESOOTHING
1) STAND-BY mode on Set.
Ordinarily, STAND-BY mode results from SHORT on LNB. Check first if TR on LNB has
stopped, and then in case that STAND-BY mode resulted from wrong software, down-load
a proper software.
POWER SWITCH
There is a TR's as a switching
role on the LNB bundle. 5V comes
out normally from Q751. If
voltage is not enough or steady,
check if the voltage is impressed
properly from Q751.
2) Screen problem in color
If you have Black-and-White screen. It mainly results from distorted 24MHz
frequency. In case of no screen display or different
color displayed, it also mainly results from the Y401 problem. Additionally, in case
that the screen display works but is with one color only, for example blue, green,
or red, it mainly results from software fault(possiblely detected only on RGB TV).
RGB Circuit
RED GREEN BLUE
Red signal input
Blue signal input
Green signal input
3) Weak TUNER signal
Check first that the voltage is impressed to LNB. If there is nothing wrong in LNB
Voltage, check if the voltage is impressed well into TUNER bundle and if data flow
out properly. If every condition is satisfied, TUNER itself can be considered to be
defective. In occasion, precise inspection should be done in case that there is
SHORT between pins(fault rarely made by a worker).
4) Screen ratio problem
If a strange ratio in 4:3 and 16:9 is detected, the voltage of TV scart pin number 8
is below 9V. In case of around 7V, screen will be shown with 16:9 ratio. In case of
over 10V, the ratio will be 4:3. If there is still a fault on screen after adjusting
screen ratio, it means the resistance of R595 on the circuit is not 1K. If the
voltage is normal but the voltage switch does not operate properly, it means that
Q593 TR is not operating normally. In addition, Q592 can affect the problem because
Q592 is a TV/sat transferring switch .
4:3-Low 0V
16:9-High 3.3V
16:9= 6V
4:3=11.3V
2 SCHEMATIC.COMPONENT LAYOUT AND BOM OF POWER SUPPLY
2.1 SCHEMATIC OF POWER SUPPLY
2.2 COMPONENT LAYOUT OF POWER SUPPLY
3 SCHEMATIC.COMPONENT LAYOUT AND BOM OF MAIN BOARD
3.1 SCHEMATIC OF MAIN BOARD
6 5 4 3 2 1
REV. HISTORY OF MODIFICATIONS CHECK.BY APP.BY DATE
1
2
BLOCK DIAGRAM Version History
V1.0: 2011-07-24 Created
TUNER LOW IF T2 DEMOD
D I2C,AGC (MSB1230)
CVBS D
I2C Y/PB/PR
TS Video buffer
DDR3 LMI RCA
(128MB)
L/R Audio OP SCART
Serial FLASH
(4MB) MSD5043-V60 SPDIF
Nand FLASH
(128MB) ESD HDMI1.3
EEPROM MII
ESD USB
(2KB)
SPI
IR PHY RJ45
POWER
C 5V/2A Front pannel C
OPTION
POWER BLOCK
VCC5V
AC/DC Front pannel
2 A
LDO VCC3_3V_PM PLL,RESET
LM1117-3.3V 50 mA FLASH
VCC12V
DC/DC 20 mA
AUDIO OP
B VCC5V_PD B
MOSFET USB/HDMI
1 A
Video Buffer
LDO VCC2_5V
LM1117-2.5V 50 mA
T2 DEMOD
DC/DC VCC1_8V_PD
TUNER
PAM2312 220 mA
DC/DC VCC3_3V_PD MSD5043
PAM2312 300 mA EEPROM
TUNER
Shenzhen Jiuzhou Electric CO.,LD
DC/DC VDDC1V2 DESCRIPTION PAGE DESCRIPTION A
A MSD5043 CORE
MP1482 1.2A DOC.NO.: MODEL NO.:
SCH P/N: PROJECT CODE:
T2 DEMOD PCB P/N: DOC. REV.: V1.1
THIS DOCUMENT IS THE PROPERTY OF Shenzhen SIGN
DESIGNED BY: Xuewei 2011-12-19 DATE
Jiuzhou Electric CO.,LD. THE CONTENTS OF THIS
DC/DC DDR1V5 DOCUMENT ARECONFIDENTIAL AND CONTSTITUTE SIGN
MSD5043 DRAWN BY:
TRADE SECERTSPROPRIETARY TO Shenzhen Jiuzhou DATE
PAM2312 250 mA DDR3 Electric CO.,LD.
CHECKED BY: SIGN
NEITHER THIS DOCUMENT NOR ITS CONTENTS SHALL
PD_CTRL BE DISCLOSED TO ANY UNAUTHORIZED PERSON. SIGN
DATE
COPIED OR PUBLISHED WITHOUT Shenzhen Jiuzhou
APPROVED BY: DATE
Electric CO.,LD.'S PRIOR WRITTEN CONSENT.
SIZE:
COPYRIGHT C 2011 Shenzhen Jiuzhou Electric CO.,LD A2 SHEET: 1 OF 11
6 5 4 3 2 1
REV. HISTORY OF MODIFICATIONS CHECK.BY APP.BY DATE
1
2
D GPIO MAPPING: D
MODE_0 USAGE USAGE DETAIL NOTE
PM_GPIO0 /FLASH_WP SFLASH
PM_GPIO1 RGB/CVBS SCART
PM_GPIO2 16:9/4:3 SCART
PM_GPIO3 TV/AV SCART
PD_CTRL PD_CTRL POWER CTRL
PM_GPIO5 ANT_PWR_CTRL TUNER
PM_GPIO6 ANT_OVERLOAD TUNER
PM_GPIO8 MUTE_CTRL AUDIO_MUTE
S_GPIO1 USB_OCD USB
S_GPIO2 /USB_CTRL USB
S_GPIO4 FE_RST DEMOD
SAR1 FP_CLK Front panel
SAR2 FP_DATA Front panel
SAR3 FP_STB Front panel
C C
B B
Shenzhen Jiuzhou Electric CO.,LD
DESCRIPTION PAGE DESCRIPTION A
A DOC.NO.: MODEL NO.:
SCH P/N: PROJECT CODE:
PCB P/N: DOC. REV.: V1.1
THIS DOCUMENT IS THE PROPERTY OF Shenzhen SIGN
DESIGNED BY: Xuewei 2011-12-19 DATE
Jiuzhou Electric CO.,LD. THE CONTENTS OF THIS
DOCUMENT ARECONFIDENTIAL AND CONTSTITUTE SIGN
DRAWN BY:
TRADE SECERTSPROPRIETARY TO Shenzhen Jiuzhou DATE
Electric CO.,LD. SIGN
CHECKED BY:
NEITHER THIS DOCUMENT NOR ITS CONTENTS SHALL DATE
BE DISCLOSED TO ANY UNAUTHORIZED PERSON. SIGN
COPIED OR PUBLISHED WITHOUT Shenzhen Jiuzhou
APPROVED BY: DATE
Electric CO.,LD.'S PRIOR WRITTEN CONSENT.
SIZE:
COPYRIGHT C 2011 Shenzhen Jiuzhou Electric CO.,LD A2 SHEET: 2 OF 11
6 5 4 3 2 1
REV. HISTORY OF MODIFICATIONS CHECK.BY APP.BY DATE
1
2
U401-A HW STRAP close MStar IC
C21
MSD5043-V60 A7
VCC3_3V_PD
D21 RF_AGC HDMI_CEC B8
IF_AGC HSYNC_/_HDMI_HDP [6] HDMI_HPD R430 NC
F20 A4 [6]
IM_Q HDMI_CH2_P HDMI-TX2P [3] R431 1K
E20
G21 IP_Q DEMOD HDMI_CH2_M
B4
C4
[6]
[6]
HDMI-TX2N CI_OEZ
CHIP_CONFIG[3]
D IM_I HDMI_CH1_P HDMI-TX1P R432 NC
G20
IP_I HDMI HDMI_CH1_M
B5
C5
[6]
[6]
HDMI-TX1N
CI_WEZ [3] R433 1K
D
HDMI_CH0_P HDMI-TX0P
F21 B6 [6] CHIP_CONFIG[2]
AVSS_MPLL HDMI_CH0_M HDMI-TX0N R434 1K
A6 [6]
HDMI_CLK_P HDMI-TXCLKP [3] R435 NC
C6 [6] HDMI-TXCLKN CI_REGZ
HDMI_CLK_M B7 [6] CHIP_CONFIG[1]
TS1/I2S_OUT_IN/SPI/EJ HDMI_SCL C7 [6]
HDMI_SCL R436 1K
U20 HDMI_SDA HDMI_SDA [3] R437 NC
TS1_CLK_/_I2S_IN_BCK_/_EJ_DINT_/_TMS_MCU CI_CEZ
U19
T20 TS1_D7_/_I2S_IN_WS_/_EJ_RST_/_TDO_MCU_/_ CHIP_CONFIG[0]
TS1_D6_/_I2S_IN_D0_/_EJ_TCK_/_RX2 C2 [3,7]
T21 DAC_B IDAC_OUT_B
TS1_D5_/_EJ_TMS C1 [3,7]
T19 IDAC_OUT_R
R21 TS1_D4_/_I2S_OUT_MUTE
TS1_D3_/_I2S_OUT_BCK
VIDEO DAC_R
DAC_G
B1
B2
[3,7]
[3,7]
IDAC_OUT_G CHIP_CONFIG[3~0]
R20 DAC_X IDAC_OUT_X
R19 TS1_D2_/_I2S_OUT_D0_/_SPI_CLK 0011: MIPS_no_EJ_NOR8
TS1_D1_/_I2S_OUT_WS_/SPI_IRQ C3 R401 0R 0100: MIPS_EJ1_NOR8
P20 AVSS_DAC_BIAS
P19 TS1_D0_/_I2S_OUT_D1_/_SPI_CSZ_/_EJ_TDO 0101: MIPS_EJ2_NOR8
N20 TS1_VLD_/_I2S_OUT_D2_/_SPI_MOSI_/_EJ_TDI
TS1_SYNC_/_I2S_OUT_MCK_/_SPI_MISO_/_EJ_T
A3 [7]
AU_LINE_L LINE_OUTL
[8] N19 A2 [7]
Debug
TS_CLK TS0_CLK AU_LINE_R LINE_OUTR
M21
TS_D7 M20 TS0_D7 VCC3_3V_PM
TS_D6
TS_D5
M19 TS0_D6
TS0_D5 TS0 AUDIO SPDIF_OUT
D3 [7]
SPDIF_OUT
L20
TS_D4 TS0_D4
L19 L401 FB/60R
TS_D3 TS0_D3 B3 CN401
K20 AU_VRM
TS_D2 TS0_D2 0603
K21 R414 R415 1
TS_D1 TS0_D1
[8] K19 10K 10K
TS_D0 J21 TS0_D0 2
TS_VAL [8] TS0_VLD
[8] J20 [3] R412 100R 3
TS_SYNC TS0_SYNC UART-RX
[3] R413 100R 4
UART-TX
[3,8] H20
IIC-SDA
IIC-SCL [3,8] H19 I2CM0_SDA
I2CM0_SCL
I2C 4PIN 2.0MM
SM/CCIR_IN_OUT/EJ
C
B9 [6]
C SC0_AUX1
SC0_AUX2
[6]
[6]
D1
D2
E2
EJ_DINT_/_CIR_D7_/_SM_C4
EJ_RST_/_CIR_D6_/_SM_C8
USB_DP_P2
USB_DM_P2
VBUS_P2
A9
B10
[6]
USB1_DP
USB1_DM
System Reset
SC0DET
SC0_5V/3V
[6]
[6] E3 EJ_TMS_/_CIR_D4_/_SM_CD
EJ_TCK_/_CIR_D5_/_SM_GPIO
USB
SC0RESET [6] F3
F2 EJ_DO_/_CIR_D3_/_SM_RST USB_DP_P0
W11
Y11
EEPROM VCC3_3V_PM
SC0CMDVCC [6] EJ_TDI_/_CIR_D2_/_SMC_VCC USB_DM_P0
[6] F1
SC0DATAIN G2 EJ_TRSTN_/_CIR_D1_/_SM_IO
SC0CLK [6] CIR_D0_/_SM_CLK VCC3_3V_PD
3
U413 R408 D401
1 8 C412 104 10K BAV99
A0 VCC
2 7 CE402 47uF/16V
1
2
A1 WP
3 6 [3,8] E
A2 SCL IIC-SCL Q401
U401-B 4
GND SDA
5 [3,8] IIC-SDA R409 1K 3906
B
AT24C64N-SC27 HIGH ACTIVE
/FLASH_WP [5]
[7]
B19
C16 PM_GPIO0 MSD5043-V60 CIR_OUT_D7_/_CI_A14
AA12
W12 C R411
[3]
RGB/CVBS
[7] B16 PM_GPIO1 CIR_OUT_D6_/_CI_A13 AA13 Device address SYS-RST
16:9/4:3 C15 PM_GPIO2 CIR_OUT_D5_/_CI_A12 Y13 100R
TV/AV [7] PM_GPIO3 CIR_OUT_D4_/_CI_A11
[10] A15 W13 E0/E1/E2=0/0/0 C415 R410 C409
PD_CTRL B15 PD_CTRL CIR_OUT_D3_/_CI_A10 Y14 10uF 10K 2.2nF
ANT_PWR_CTRL [8] PM_GPIO5 CIR_OUT_D2_/_CI_A9 WRITE=A0H
[8] D14 W14 0805
ANT_OVERLOAD D16 PM_GPIO6 CIR_OUT_D1_/_CI_A8 Y15 READ=A1H
[10]
STATE D15 PM_GPIO7 CIR_OUT_D0_/_CI_A7 AA15
[7]
MUTE_CTRL PM_GPIO8 CIR_OUT_CLK_/_CI_A6
POWER_KEY [10]
[10]
E17
A16 PM_GPIO9 GPIO NF_RBZ_/_CI_A5
Y21
AA19
[5]
[5]
NF_RBZ
IR IRIN NF_REZ_/_CI_A2 W19 NF_REZ
NF_CEZ [5]
NF_CEZ
C20 W18 CRYSTAL
NAND/CCIR_IN_OUT/CI
[5]
[10] B17 SAR0 NF_CLE_/_CI_A3 Y19 [5]
NF_CLE
FP_CLK NF_ALE
[10] C17 SAR1 NF_ALE_/_CI_A0 Y20 [5]
FP_DATA
[10] D17 SAR2 NF_WEZ_/_CI_A1 AA20 [5]
NF_WEZ
FP_STB SAR3 NF_WPZ_/_CI_A4 AA18 NF_WPZ R403 33R
NF_D0_/_CI_D0 [5] NF_D0 [3] OSC_XOUT
[9] C10 Y18 [5] R402 1M R405 0R
ETH_RST A10 VSYNC_/_ET_RST NF_D1_/_CI_D1 W17 NF_D1 [3]
[5] OSC_XIN
B FE_RST [8] N21 SPDIF2_/_GPIO
R18 S_GPIO4
Y10 S_GPIO3
NF_D2_/_CI_D2
NF_D3_/_CI_D3
NF_D4_/_CI_D4
Y17
W16
Y16
[5]
[5]
NF_D2
NF_D3
NF_D4
Y401 24MHz B
/USB_CTRL [6] [5]
[6] W10 S_GPIO2 NF_D5_/_CI_D5 AA16 [5]
NF_D5 CRYSTAL SPEC:
USB_OCD G3 S_GPIO1 NF_D6_/_CI_D6 W15 [5]
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