Service Manuals, User Guides, Schematic Diagrams or docs for : Samsung Monitor Samsung_PN50A550_PN58A550_SchematicDiagram_[SM]
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Schematic Diagram
7. SchematicDiagram
7-1 CircuitDescription
Logic Board Y Main Board X Main Board
Display Row
DRAM Data Driver
PDP Panel
Input X-Pulse
Data
Data Display Generator
Controller Driver
Processor Timing Y-Pulse
Timing
Controller Generator
Scan
Timing
Address Buffer
SMPS Board
LVDS
Main SMPS
Main Board
LVDS Image Audio
Deinterlacer
Trans Enhancer Processor
Image CPU Video Speaker
Decoder Decoder Out
AC Power
Scaler
Tuner Source
TMDS A/D Video
Converter S/W Micom
Recever
SMPSBoard
The SMPS used for the PDP has been designed to be efficient, compact and lightweight. For VS and VA outputs, a LLC converter
has been used. For the other outputs, a Flyback converter has been used.
LOGICBoard
The logic circuit consists of a Logic Main Board and an Address Buffer Board. The Logic Main Board decodes the video signal
encoded by the Video Board, outputs the ADDRESS data signal for each pattern and generates X and Y drive signals. The Address
Buffer Board buffers and transfers the ADDRESS data output signal using TCP IC.
- LVDS with built-in video signal processing (W/L, error diffusion, APC, FCR, etc.) applied and 1 ASIC chip.
- Outputs the address Drive IC control and data signals to the Buffer Board.
- Outputs the control signal for the X and Y Drive Boards.
- Monitors major drive voltages (Micom Circuit Block); detects if a surge voltage has been applied and protects the Drive Circuit.
- Temperature Adaptive Operating Mode (Low Temperature/Room Temperature/High Temperature); Discharge optimization for
each temperature level.
X-MAINBoard
Connects to the X terminal block, 1) provides maintaining voltage waveform (including ERC), and 2) maintains the Ve bias in the
Scan section.
Y-MAINBoard
Connects to the Y terminal block, 1) provides maintaining voltage waveform (including ERC), 2) provides Y Rising, Falling Ramp
waveforms, and 3) maintains the Vscan bias.
AddressBufferBoard
It delivers the data signal and control signal to the TCP.
Samsung Electronics 7-1
MEMO
7-2 Samsung Electronics
Schematic Diagram
7-2 SchematicDiagram
7-2-1 Power
Power LOCATION SUFFIX
STANDBY POWER PDP P OPTION C
STB3.3V LCD L SIDEAV S
STB5V TP101 TP102
DELETE D ON BOARD B
IC105
BD100 AP1117D-33A
3 VIN VOUT
2
HOTEL H FUNCTION I2S I
ADJ
C101
10UF
1
10V
R101L
1KOHM
INV_HSYNC
CN101
3
R102L
SMW200-24C 4.7KOHM
TP103 Q100L C
B 2 SW_POWER
KSC1623-Y
A1.2V
E
1
2
1
3 R103P D3.3V A2.5V D3.3V
4 TP104
TP105 B12VS
M ND1
5 0OHM
6
G
IC106 IC107
7 FAN1112S
8 LF25CDT
9 PDP OPTION 1 3 1 OUT 3
IN OUT
10 D3.3V IN OUT
2
GND
11 GND C111 C112
12 TP107
10UF 10UF
13
2
TP106 10V 10V
2
14 B5V
1
15 BD101 TP108
16
L100
17
18
19 C104
20 10NF
21 50V IC101 C105
D100 C139
100NF C108
22 B13V D103 75V
MP2363DN
16V
10NF
10UF
23 1 8 R104 50V
BS SS 10V
24 2 7 39KOHM
IN EN
TP109 PMLL4148 3 SWCOMP 6 R105
4 5 10KOHM
GNDFB2
C102 C103
C138
10UF 100NF
M ND1
10UF
10V 16V
10V
G
TP110 R106
2.7KOHM R107
15KOHM
C107
10NF
50V
D3.3V D1.8V
M ND1
G
IC104
SPX1587AT-L/TR BD102
1 OUT 3
IN OUT
C117 C118 C119 C120 C121 C122 C123 C124
C113 GND C115 C116 100NF 100NF 100NF 100NF 100NF 100NF 100NF 100NF
OPTION PANLE R116 C114
10UF 1KOHM 10UF 1UF 25V 25V 25V 25V 25V 25V 25V 25V
10UF
BD104,R112 5V INPUT 10V 1/10W 10V 10V
2
PANEL_VCC 10V
BD105,R113 13V INPUT R117
TP111
430OHM
IC103L 1/10W C125 C126 C127 C128 C129 C130
BD104D SI4435DY 100NF 100NF 100NF 100NF 100NF 100NF
1 8 25V 25V 25V 25V 25V 25V
2 7
R110L C109L 3 6
100KOHM 1UF 4 5
BD105L 25V
R112D R113L
10KOHM 47KOHM
R111L
3
10KOHM R120D
R126
SW_PVCC
2 B
C
Q101L 10KOHM 100OHM
KSC1623-Y
E B5V POWER_DET
H:POWER ON
1
L:OFF IC102 C134
MP2363DN
100NF 25V
B9V_SPLITTER B8V BD103 1 BS SS 8
2 IN EN 7
TP112 3 6
SWCOMP R121
C133 4 5
GNDFB2 1KOHM
IC108 100NF
BD106 BA178M09FP D104 C132 25V
C131
M ND1
10NF C135
1 IN OUT
3 10UF 10NF
50V
G
10V 50V
GND LL4148
C110
10UF
16V
2
R124
0OHM
CORE1.1V
L101
C140
R122 C137
10NF
2KOHM 10UF
D102 50V
10V
X110 X111 X112 X113
BN61-03858A BN61-03858A BN61-03858A BN61-03858A
R123
10KOHM
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
1
2
3
4
5
Samsung Electronics 7-3
Schematic Diagram
7-2-2 SoundProcessing
This Document can not be used without Samsung's authorization.
Power
SUB FUNCTION I/F
TOUCH I2C
DISCRETE
0OHM 1/10W
DISCRETE
IR
STB3.3V R293I
STANDBY MICOM
KEY_INPUT1
R295I
KEY_INPUT2
0OHM 1/10W
STB5V
M BD4 1 4 8 SE
M BD4 1 4 8 SE
M BD4 1 4 8 SE
L200
STB5V 10UH R202 R203
RESET & POWER DETECTION 1.5KOHM 1.5KOHM
100V
100V
100V
M
M
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