Service Manuals, User Guides, Schematic Diagrams or docs for : Sony Ericsson Mobile Phones Сотовый телефон Sony Ericsson S500 & W580 SONY ERICSSON S500, W580 5
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The routing of BTCLK_IN should be done with extra care, i.e to avoid noisy
signals. It is crucial that the reference clock supplied to BT is free of BTRX_1
noise to be able to guarantee a good radio performance. BTRX
Especially cross talks from surrounding digital signals must be avoided.
BTCTS
BTCTS
BTRESn
R1002
L1000 10Kohms
6.8uH CLKREQ
BTCLK BTCLK_IN CLKREQ
BTCLK REP621105/1
REG704494/68
RJC4633012/1
RJC4633012/1
R1004
D1000 100Kohms
C1000 C1001 REP621106/1
10pF 10pF BT-FUNCTIONAL
CLOCK AND RESET
D3
RESETn
BTCLK_IN D6
REF_CLK_IN
G3
LP_CLK
RTCCLK
SW INITIATED LOW POWER MODE
C5 F7 R1001
BT_WAKEUP HOST_WAKEUP/SPI_INT 0ohms BTANT
BTANT
REP622001/0
UART INTERFACE
RJC4633011/1
RJC4633011/1
BTTX F5 F6 C1014 C1003
UART_RXD/SPI_DI UART_TXD/SPI_DO
BTTX 1pF 1pF
BTRTS G4 F4
UART_CTS/SPI_CLK UART_RTS/SPI_CSN
BTRTS
PCMCLK D1 PCM INTERFACE
PCM_CLK
PCMCLK
PCMSYN C2 D1000
PCM_SYNC
PCMSYN
PCMDATB D2 BT-SUPPLY
PCM_A
PCMDATB VBT27
PCMDATA E1 VBT27 net split to A7 and G1
PCM_B
PCMDATA close to regulator DIGITAL GROUND
POWER SUPPLY
A7 VDD_HV_A 2.75V
JTAG/GPIO G1
VDD_HV_D
B3 E3
JTAG_NTRST/GPIO_16 VSS_DIG
C3 VDDE18 E4
JTAG_TCK/GPIO_8 VSS_DIG
B2
JTAG_TDO/GPIO_11
B1
JTAG_TDI/GPIO_9
1V65 to 2V85
C1 G5
JTAG_TMS/GPIO_10 VDD_IO_A IOs SUPPLY
D5
GEN_PURPOSE/GPIO_0
VRTC13
E6 C4
CLK_REQ_IN_1 CLK_REQ_OUT_1 1V17 to 2V85
F3 VDD_IO_B
G6 G7 IOs SUPPLY
CLK_REQ_IN_2 CLK_REQ_OUT_2 'VSS_RF' should be separated from other VSS,
RJC5163016/1
RJC5163016/1
RJC5163016/1
RJC5163016/1
with a clearance of min 0.2mm, on the top layer,
C1004 C1005 C1006 C1008 1V65 to 2V85
E7 first and second internal layer.
100nF 100nF 100nF 100nF VDD_CLD SYSTEM CLOCK
VDDE18 CONFIGURATION RF Z1000 SUPPLY
PINS The 'VSS' of the B-BPF and the BT antenna should also be
Freq connected to this 'VSS_RF.'
RFP A3 4 1
CONFIG_1 BAL UNBAL
E2
A4 5 2 ANALOG GROUND
CONFIG_2 BAL BAL_DC-FEED
F1 RFN B4
3 6 VSS_ANA
CONFIG_3 GND GND C1006 close to G1
F2 B6
VSS_ANA
C1008 close to A7 C6
DEA212450BT-7031A1 VSS_ANA
TEST-PIN RTN202939/1
LEAVE UNCONNECTED 2.4GHz
AF_PRG
E5
Do not connect! INTERNAL SUPPLY RF GROUND
DECOUPLING
RYT123923/2 B7
STLC2500C4 VDD_DSM
C7
VDD_N
A2
D7 VSS_RF
VDD_CL
A5
A1 VSS_RF
VDD_RF
RJC5164016/22
RJC5164016/22
RJC5164016/22
RJC5164016/22
C1009 C1010 C1011 C1012
220nF 220nF 220nF 220nF TEST PINS
B5
TOUT_IN_QP
A6
TOUT_IP_QN
C1009 - 1012 close to chip
OUTPUT
REGULATOR
FOR CORE LOGIC
Regulator internally connected
VDD_D G2
RJC5164016/22
C1013
RYT123923/2 220nF C1013 close to G2
STLC2500C4
VBT27 VDDE18 VRTC13
VBT27 Confidential
VDDE18 Approved according to 00021-LXE 107 42/1 SCHEMA DIAGRAM
VRTC13
Sony Ericsson RT/SEMC/BGRRHP Christian Lindqvist
RT/SEMC/BGRRHD Norbert Ingram 3/6/2007 D
Bluetooth SCHEMATIC
3/1911-ROA 128 2290 Uen 1 of 1
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