Service Manuals, User Guides, Schematic Diagrams or docs for : TOSHIBA LCD 55WL863 toshiba-vl863-PE0993
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5T03655-2E
SCHEMATIC DIAGRAMS
PRODUCT NAME VL863/WL863
UNIT NAME MAIN UNIT NO. PE0993
PWA NAME PWA NO.
PWB NAME PWB NO.
PAGE FUNCTION REV PAGE FUNCTION REV PAGE FUNCTION REV PAGE FUNCTION REV
1 SEINE5L I2C/SD/USB/JTAG 26 SPI FLASH 51 CONNECTOR AVJACK 76 TVM(FAN CONTROL)
2 SEINE5L DDR 27 EBUS NAND FLASH 52 DSUB15P PC IN 77 TVM(LED/RMT/RGB/TOUCH)
3 SEINE5L EBUS/SPI 28 L2SW (MISC.) 53 78 TVM(PANEL I/F)
4 SEINE5L UART/ETHER 29 L2SW (RMII I/F) 54 EURO SCART OUT 79 TVM(PIR)
5 SEINE5L TS 30 RJ45 CONNECTOR 55 AV INPUT1 80 TVM(KEY CONNECTOR)
6 SEINE5L MCU 31 WLAN I/F 56 AV INPUT2 81 TUNER
7 SEINE5L AUDIO 32 WLAN POWER 57 AV INPUT3 82 SYNC_DET(TV_OUT)
8 SEINE5L LVDS OUT 33 USB CONNECTOR 58 SYNC DETECT 83 TUNER DVB-S/S2
9 SEINE5L HDMI/DAC 34 USB HUB 1/2 59 PANEL I/F LVDS OUT 84 DEMOD DVB-T/C
10 SEINE5L ADC 35 USB HUB 2/2 60 PANEL I/F LVDS OUT 85 DEMOD DVB-T2/T/C
11 SEINE5L ANALOG POWER 36 USB POWER 61 PANEL I/F DIMMER CON 86 DEMOD DVB-S2/S
12 SEINE5L DIGITAL IO POWER 37 AUDIO RESISTOR 62 PANEL I/F POWER 87 DiSEqC LNB POWER
13 SEINE5L MEMORY POWER 38 AUDIO I2S CLK 63 HDMI Connector 88 TUNER POWER
14 SEINE5L DIGITAL POWER 39 AUDIO MUTE 64 HDMI SW 1/3 89 CI TS_SELECTOR
15 SEINE5L BOOT-CONFIG 40 AUDIO SIF 65 HDMI SW 2/4 90 CI POWER/CONNECTOR
16 SEINE5L XTAL/VREF 41 AUDIO DAC (HEADPHONE) 66 HDMI SW 3/4 91 CI ADDRESS BUFFER
17 SEINE5L PLL/DAC 42 AUDIO Linedrivr(TVOUT) 67 HDMI SW 4/4 92 CI DATA BUFFER
18 SEINE5L CAPACITOR 43 AUDIO CONNECTOR 68 HDMI ARC 93 CI CONTROL BUFFER
19 SEINE5L PWR-REG 44 AUDIO DSP(CIRRUS) 69 HDMI Power 94 CI TS OUTPUT BUFFER
20 PERI (CLK/VCXO) 45 AUDIO D-AMP 70 HDMI TX PWR5 95 POWER 1.5V
21 PERI (PIO/IRQ) 46 AUDIO AMP FILTER 71 HDMI TX PWR5 96 POWER 1.1V
22 PERI (I2C/UART) 47 AUDIO D-AMP (Woofer) 72 TVM(MICON) 97 POWER 3.3V
23 DDR3 SDRAM 48 AUDIO AMP FILTER (Woofer) 73 TVM(MICON2) 98 POWER 6V/5V
24 DDR3 VTT 49 Headphone AMP 74 TVM(RESET I2C) 99 POWER CONNECTOR
25 EBUS RESISTOR 50 EURO SCART 75 TVM(CEC) 100 EMC CONTROL
APPROVED BY CHECKED BY DESIGNED BY TITLE TOTAL PAGE NO. REV.MARK DRAWING.NO.
IWANO IWANO SHIMIZU CIRCUIT DIAGRAM 100 TITLE PP
2011.03.11 09:37 TOSHIBA CORPORATION
5T03655D
1 2 3 4 5 6 7 8
V46A00062200
A A
DTV SYSTEM LSI 1/14
[V-U90432]
IC100
790 M_TSI3DATA1 AF3
AF2 STCCLKI2/TSI3DATA1/PIO95 STCPWM2/TSI3DATA2/PIO0 AJ2
AH2
M_TSI3DATA2 790
STCCLKI1 STCPWM1/PIO1
120 M_STCCLKI0 AF1 STCCLKI0 STCPWM0 AG1 M_STCPWM0 120
120 M_PANELCLK AH1 PANELCLKI [TP]
DP103
701 134 C_HOSTRST AE1
AE2 SOC_RESET_N WDT_RESETOUT_N/PIO4 AG2 1
CPU_RESET_N AM29 M_BL0PWM 652
BL0PWM/PIO2
10nF(K) 1 902 M_VID AJ29 VID BL1PWM/PIO3 AL29 M_BL1PWM 652
C1000
[TP]
B DP114
1[TP] B
DP112 [IRQ]
2 1
795 M_CIIREQ_N G30
AK6 IRQ5/CIIREQ_N/PIO46
GND IRQ4/PIO47/CIRESET1
GND AL6 IRQ3/PIO48/CICS1_N
AM6 IRQ2/PIO49
AL5 IRQ1/PIO50
662 H_HDMISW_INT AM5 IRQ0/PIO51
[I2C]
370 662 124 M_I2CDATA0 AN4 I2CDATA0/PIO54 I2CDATA2/PIO58 AN6 M_I2CDATA2 124 650
370 662 124 M_I2CCLK0 AP4 I2CCLK0/PIO55 I2CCLK2/PIO59 AP6 M_I2CCLK2 124 650
750 775 372 705 707 124 350 760 765 770 M_I2CDATA1 AN5 I2CDATA1/PIO56 CI2CDATA/PIO60 AN29 M_CI2CDATA 124 650
M_I2CCLK1 AP5 AP29 M_CI2CCLK
C 750 775 372 705 707 124 350 760 765 770 I2CCLK1/PIO57 CI2CCLK/PIO61 124 650 C
[SD I/F]
122 M_SDCLKB D33 SDCLKB L when unused Open when unused SDCLK E34
122 M_SDCD F34 SDCD PU when unused Open when unused SDCLKF D34
122 M_SDWP F33 SDWP PU when unused Open when unused SDCMD E33
E32
Open when unused SDDATA0 E31
Open when unused SDDATA1 F32
Open when unused SDDATA2 F31
3.3VD Open when unused SDDATA3 F30
Open when unused SDPWR G32
Open when unused SDV18EN
[USB]
D R1112 E14 A14 M_USB0DP 161 D
1 2 D14 USB0CLK USB0DP B14 M_USB0DM 161
USB0OVERC USB0DM
4.7K(D) 116 M_USB0REXT H16 USB0REXT USB0PW D15
H15
M_USB0PW 161
L USB0TEST
E15 USB1CLK USB1DP A15 M_USB1DP 160
163 M_USB1OVERC C15 USB1OVERC/PIO63 USB1DM B15 M_USB1DM 160
116 M_USB1REXT H18 USB1REXT USB1PW/PIO62 C16
H17
M_USB1PW 163
L USB1TEST
[EJTAG]
AK29 DBGTCK DBGTDO AL30
AK30 DBGTDI
AJ30 DBGTMS
E AH30 DBGTRST_N GND E
TC90432MBG(OF1203)
F F
DESIGNED BY TITLE FUNCTION SH.NO. PAGE NO. REV.MARK DRAWING.NO.
T.SHIMIZU MAIN UNIT S5L I2C/SD/USB/JTAG 101 1 PP PE0993
2011.03.11 09:37 TOSHIBA CORPORATION
5T03655D
1 2 3 4 5 6 7 8
A V46A00062200 A
DTV SYSTEM LSI 2/14
[V-U90432]
IC100
[DDR]
127 M_DDRDQ31 AK26 DDRDQ31 DDRAD15 AN14
127 M_DDRDQ30 AP27 DDRDQ30 DDRAD14 AP14
127 M_DDRDQ29 AJ25 DDRDQ29 DDRAD13 AK17 M_DDRAD13 127 130
127 M_DDRDQ28 AN25 DDRDQ28 DDRAD12 AN15 M_DDRAD12 127 130
127 M_DDRDQ27 AP26 DDRDQ27 DDRAD11 AL17 M_DDRAD11 127 130
M_DDRDQ26 AK25 AL16 M_DDRAD10 B
B 127
127 M_DDRDQ25 AN26 DDRDQ26
DDRDQ25
DDRAD10
DDRAD9 AN16 M_DDRAD9 127
127
130
130
127 M_DDRDQ24 AL26 DDRDQ24 DDRAD8 AN19 M_DDRAD8 127 130
127 M_DDRDQ23 AK23 DDRDQ23 DDRAD7 AP15 M_DDRAD7 127 130
127 M_DDRDQ22 AN24 DDRDQ22 DDRAD6 AN20 M_DDRAD6 127 130
127 M_DDRDQ21 AJ22 DDRDQ21 DDRAD5 AL15 M_DDRAD5 127 130
127 M_DDRDQ20 AP23 DDRDQ20 DDRAD4 AL18 M_DDRAD4 127 130
127 M_DDRDQ19 AN23 DDRDQ19 DDRAD3 AP16 M_DDRAD3 127 130
127 M_DDRDQ18 AK22 DDRDQ18 DDRAD2 AP19 M_DDRAD2 127 130
127 M_DDRDQ17 AP24 DDRDQ17 DDRAD1 AK16 M_DDRAD1 127 130
127 M_DDRDQ16 AL23 DDRDQ16 DDRAD0 AK19 M_DDRAD0 127 130
127 M_DDRDQ15 AN12 DDRDQ15
127 M_DDRDQ14 AK13 AP17 M_DDRCLK0
127 M_DDRDQ13 AP13 DDRDQ14
DDRDQ13
DDRCLK0
DDRBCLK0 AN17 M_DDRBCLK0 127 130
127 130
127 M_DDRDQ12 AJ14 DDRDQ12
127 M_DDRDQ11 AK14 AP18 M_DDRCLK1
127 M_DDRDQ10 AN13 DDRDQ11
DDRDQ10
DDRCLK1
DDRBCLK1 AN18 M_DDRBCLK1 127 130
127 130
M_DDRDQ9 AL13
C 127
127 M_DDRDQ8 AP12 DDRDQ9
DDRDQ8 DDRCKE AL21 M_DDRCKE 127 130 C
127 M_DDRDQ7 AP9 DDRDQ7 DDRCS_N AN21 M_DDRCS0_N 127 130
127 M_DDRDQ6 AK10 DDRDQ6 DDRRAS_N AP21 M_DDRRAS_N 127 130
127 M_DDRDQ5 AN11 DDRDQ5 DDRCAS_N AP20 M_DDRCAS_N 127 130
127 M_DDRDQ4 AJ11 DDRDQ4 DDRWE_N AK20 M_DDRWE_N 127 130
127 M_DDRDQ3 AK11 DDRDQ3
127 M_DDRDQ2 AP10 DDRDQ2 DDRBA2 AL20 M_DDRBA2 127 130
127 M_DDRDQ1 AL10 DDRDQ1 DDRBA1 AL19 M_DDRBA1 127 130
127 M_DDRDQ0 AN10 DDRDQ0 DDRBA0 AN22 M_DDRBA0 127 130
127 130 M_DDRRESET AK18 DDRRESET_N DDRDM3 AN27
AP25
M_DDRDM3 127
M_DDRDM2 127
DDRDM2
127 130 M_DDRODT AP22 DDRODT DDRDM1 AP11
AN9
M_DDRDM1 127
M_DDRDM0 127
AH17 DDRDM0
DDRZQ AM27 M_DDRDQS3
DDRDQS3 127
D 127 130 M_DDRVREF AH13
AH23 DDRVREF0 DDRDQS2 AM24
AM12
M_DDRDQS2
M_DDRDQS1 127 D
1.1V_DDRPLL DDRVREF1 DDRDQS1 AM9 M_DDRDQS0 127
AH18 DDRDQS0 127
PLLAVD0 M_DDRDQSN3
10nF(K)
10nF(K)
10nF(K)
2 2 2 AJ18 PLLAVD1 DDRDQSN3 AL27 127
C1232
C1233
C1234
DDRDQSN2 AL24 M_DDRDQSN2 127
DDRDQSN1 AL12 M_DDRDQSN1 127
AL9 M_DDRDQSN0
1
DDRDQSN0 127
240(D)
1 1 1
R1152
TC90432MBG(OF1203)
2
GND
GND
E E
F F
DESIGNED BY 2 0 1 1 / 0 2 / 1 0 TITLE FUNCTION SH.NO. PAGE NO. REV.MARK DRAWING.NO.
T.SHIMIZU MAIN UNIT S5L DDR3 102 2 PP PE0993
2011.03.11 09:37 TOSHIBA CORPORATION
5T03655D
1 2 3 4 5 6 7 8
A A
V46A00062200
B B
DTV SYSTEM LSI 3/14
[V-U90432]
IC100
A19 EBCLKI EBCLKO A20
131 M_EBDAT15 E25 EBDAT15/CIREG_N EBADD8/CIDATA7/NAALE A26 M_EBADD8 131
131 M_EBDAT14 A24 EBDAT14/CIADD14 EBADD7/CIDATA6/NACLE B26 M_EBADD7 131
131 M_EBDAT13 B24 EBDAT13/CIADD13 EBADD6/CIDATA5 C26 M_EBADD6 131
115 131 M_EBDAT12 C24 EBDAT12/CIADD12 EBADD5/CIDATA4 D26 M_EBADD5 131
115 131 M_EBDAT11 D24 EBDAT11/CIADD11 EBADD4/CIDATA3 A25 M_EBADD4 131
115 131 M_EBDAT10 E24 EBDAT10/CIADD10 EBADD3/CIDATA2 B25 M_EBADD3 131
115 131 M_EBDAT9 A23 EBDAT9/CIADD9 EBADD2/CIDATA1 C25 M_EBADD2 115 131
115 131 M_EBDAT8 B23 EBDAT8/CIADD8 EBADD1/CIDATA0 D25 M_EBADD1 115 131
131 M_EBDAT7 C23 EBDAT7/CIADD7/NADAT7
M_EBDAT6 D23 E21 M_CICS_N 794
C 131
131 M_EBDAT5 E23 EBDAT6/CIADD6/NADAT6
EBDAT5/CIADD5/NADAT5
EBCE2_N/CICS_N/PIO52
EBCE1_N/NACE_N D21 M_NACE_N 131 C
131 M_EBDAT4 A22 EBDAT4/CIADD4/NADAT4 EBCE0_N C21
131 M_EBDAT3 B22 EBDAT3/CIADD3/NADAT3
131 M_EBDAT2 C22 EBDAT2/CIADD2/NADAT2 EBBE1_N/CIIORD_N/NARE_N B21 M_CIIORD_N 795
131 M_EBDAT1 D22 EBDAT1/CIADD1/NADAT1 EBBE0_N/CIIOWR_N/NAWE_N A21 M_CIIOWR_N 795
131 M_EBDAT0 E22 EBDAT0/CIADD0/NADAT0
EBWE_N/CIWE_N E20 M_EBWE_N 131
131 M_NABSY_N B19 EBINT/NABSY_N EBOE_N/CIOE_N D20 M_EBOE_N 131
131 M_NAWE_N C20 EBWAIT_N/NAWE_N/PIO53 B20 M_NARE_N 131
NARE_N/EBAVD_N
[SPI]
132 M_SPI_MOSI P34 SPI_MOSI/MCU_PI1 SPI_CLK N34 M_SPICLK 132
132 M_SPI_MISO P33 SPI_MISO/MCU_PI2
M_SPI_IO2 R34 M34 M_SPI_CS0 132 D
D 132
132 M_SPI_IO3 R33 SPI_IO2/MCU_PI3 SPI_CS0_N N33
1
SPI_IO3/MCU_PI4 SPI_CS1_N/MCU_PI0
DP105
[TP]
TC90432MBG(OF1203)
E E
F F
DESIGNED BY 2 0 1 1 / 0 2 / 1 0 TITLE FUNCTION SH.NO. PAGE NO. REV.MARK DRAWING.NO.
T.SHIMIZU MAIN UNIT S5L EBUS/SPI 103 3 PP PE0993
2011.03.11 09:37 TOSHIBA CORPORATION
5T03655D
1 2 3 4 5 6 7 8
A A
V46A00062200
B DTV SYSTEM LSI 4/14 B
[V-U90432]
IC100
[UART]
DP108
[TP]
E30 UACTS0_N/TSI1DATA5/PIO7 UARTS0_N/TSI1DATA4/PIO6 D30
124 M_UARXD0 B31
A31 UARXD0 UATXD0 C30 M_UATXD0 124
UA0EXCLK/PIO8
1
795 M_CIRESET C31 UACTS1_N/CIRESET/PIO12 UARTS1_N/CIRD_N/PIO11 B32 M_CIRD_N
M_CICD2_N 794
795 M_CICD1_N B34 UARXD1/CICD1_N/PIO9 UATXD1/CICD2_N/PIO10 B33 795
795 M_CIWAIT_N A32 UA1EXCLK/CIWAIT_N/PIO13
D31 UACTS2_N/TSI1DATA7/PIO15 UARTS2_N/TSI1DATA6/PIO14 D32
C33 UARXD2 UATXD2 C32
C34 UA2EXCLK/TSO0DATA5/PIO16
C AK7 AL7 M_TSI3DATA7 C
M_UA_TVM2SOC
701 124 M_TSI3DATA3 AN7 UACTS3_N/TSO1CLKO/PIO18
UARXD3
UARTS3_N/TSO1CGMS/TSI3DATA7/PIO17
UATXD3 AM7 M_UA_SOC2TVM 790 124
701
790 AP7 UA3EXCLK/TSI3DATA3/PIO19
[ETHER]
151 M_ETREFCLK A17 ETREFCLK ETMDC D16
E16
M_ETMDC
M_ETMDIO 150
ETMDIO 150
B17 ETRXC OPEN WHEN RMII MODE OPEN WHEN RMII MODE ETTXC A18
151 M_ETRXD0 C17 ETRD0 ETTD0 B18 M_ETTXD0 151
151 M_ETRXD1 D17
E17 ETRD1 ETTD1 C18
C19
M_ETTXD1 151
D18 ETRD2 OPEN WHEN ERR IS NOT USED OPEN WHEN RMII MODE ETTD2 D19
ETRD3 OPEN WHEN RMII MODE OPEN WHEN RMII MODE ETTD3
151 M_ETCRS_DV E18 ETRXCTL ETTXCTL E19 M_ETTXEN 151
D D
[PCI EXPRESS]
G31 PCIERST_N/PIO64 OPEN WHEN UNUSED
K34 PCIERXSIP OPEN WHEN UNUSED OPEN WHEN UNUSED PCIETXSON H34
K33 PCIERXSIN OPEN WHEN UNUSED OPEN WHEN UNUSED PCIETXSOP H33
H31 PCIECKREFP OPEN WHEN UNUSED
H30 PCIECKREFN OPEN WHEN UNUSED OPEN WHEN UNUSED PCIEAMOUT H32
TC90432MBG(OF1203)
E E
F F
DESIGNED BY 2 0 1 1 / 0 2 / 1 0 TITLE FUNCTION SH.NO. PAGE NO. REV.MARK DRAWING.NO.
T.SHIMIZU MAIN UNIT S5L UART/ETHER 104 4 PP PE0993
2011.03.11 09:37 TOSHIBA CORPORATION
5T03655D
1 2 3 4 5 6 7 8
A A
V46A00062200
DTV SYSTEM LSI 5/14
[V-U90432]
IC100
[TS I/F]
663 H_EXT_RESET AK2 TSI5DATA/TSO1DATA/PIO32 TSO1DATA/TSI1DATA1/PIO41 B27
H_VCC_EN AK3 C27 B
B 668
668 H_CD_SENSE AK4 TSI5VALID/TSO1VALID/PIO33
TSI5SYNC/TSO1SYNC/PIO34
TSO1VALID/TSI1DATA2/PIO42
TSO1SYNC/TSI1DATA3/PIO43 D27
667 H_EN_RPWR4 AK1 TSI5CLKI/PIO35 TSO1CLKO/TSO0DATA6/PIO44 A27
TSO1CGMS/TSO0DATA7/PIO45 E26
790 M_TSI3DATA4 AL2 TSI4DATA/TSI3DATA4/PIO28
790 M_TSI3DATA5 AL3 TSI4VALID/TSI3DATA5/PIO29 TSO0DATA/PIO36 B28
790 M_TSI3DATA6 AL4 TSI4SYNC/TSI3DATA6/PIO30 TSO0VALID/PIO37 C28
667 H_EN_VBUS4 AL1 TSI4CLKI/PIO31 TSO0SYNC/PIO38 D28
TSO0CLKO/PIO39 A28
790 M_TSI3DATA AM2 TSI3DATA/PIO24 TSO0CGMS/TSO0DATA1/PIO40 E27
790 M_TSI3VALID AM3 TSI3VALID/PIO25
790 M_TSI3SYNC AM4 TSI3SYNC/PIO26
790 M_TSI3CLKI AM1 TSI3CLKI/PIO27
AN2 TSI2DATA
AN3 TSI2VALID
AP3 TSI2SYNC
AN1 C
C TSI2CLKI
B29 TSI1DATA
E28 TSI1VALID
E29 TSI1SYNC
A29 TSI1CLKI
B30 TSI0DATA/TSO0DATA2/PIO20
C29 TSI0VALID/TSO0DATA3/PIO21
D29 TSI0SYNC/TSO0DATA4/PIO22
A30 TSI0CLKI/PIO23
AJ1 TSOXCLKI
[DEMOD]
120 M_XIN AD1 XIN XOUT AD2
D V1 AE3 D
V2 VINP_VSB 0.1uF When Unused Open When Unused OFDM_IFAGC AE4
VINN_VSB 0.1uF When Unused Open When Unused OFDM_RFAGC Y7
Y1 0.1uF When Unused VBGF
Y2 JAD1_QP 0.1uF When Unused AE5
W1 JAD1_QN 0.1uF When Unused Open When Unused PSK_AGC AA7
W2 JAD1_IP 0.1uF When Unused 0.1uF When Unused VCM_8PSK
JAD1_IN 0.1uF When Unused
TC90432MBG(OF1203)
100nF(K)
100nF(K)
100nF(K)
100nF(K)
100nF(K)
100nF(K)
100nF(K)
100nF(K)
1 1 1 1 1 1 1 1
C1210
C1211
C1212
C1213
C1214
C1215
C1216
C1217
E 2 2 2 2 2 2 2 2 E
GND GND
F F
DESIGNED BY 2 0 1 1 / 0 2 / 1 0 TITLE FUNCTION SH.NO. PAGE NO. REV.MARK DRAWING.NO.
T.SHIMIZU MAIN UNIT S5L TS 105 5 PP PE0993
2011.03.11 09:37 TOSHIBA CORPORATION
5T03655D
1 2 3 4 5 6 7 8
A A
V46A00062200
3.3VD
2
4.7K(D)
DTV SYSTEM LSI 6/14
R1168
[V-U90432]
IC100
[MCU]
1
120 M_XIN12M Y34
AA32 MCU_XIN12M MCU_XOUT12M Y33
AA31
M_XOUT12M 120
MCU_XIN32K PD When Unused Open When Unused MCU_XOUT32K
B W34 MCU_RESET_N Open When Unused Open When Unused MCU_RESETOUT_N Y32 B
701 C_COLDRST W33 COLDRESET_N
U33
10nF(K)
1 U34 MCU_PA0_TMS (-) Open When Unused
C1001
V34 MCU_PA1_TCK (-) Open When Unused
M_EBADD16 V33 MCU_PA2_TRACECLK/EBADD15 (-) Open When Unused
115 M_EBADD17 V32 MCU_PA3_TRACE0/EBADD16 (-) Open When Unused
2 115 M_EBADD18 V31 MCU_PA4_TRACE1/EBADD17 (-) Open When Unused
115 M_EBADD19 W32 MCU_PA5_TRACE2/EBADD18 (-) Open When Unused
115 W30 MCU_PA6_TRACE3/EBADD19 (-) Open When Unused W31
Y30 MCU_PB1_TDI (-) Open When Unused (-) MCU_PB0_TDO
GND MCU_PB2_TRST_N (-) Open When Unused
M_HEAD W29 T30 H_ARC0_OFF
701 124 C_HOTSTART Y29 MCU_PD0_ADIN0/PIO73 (PD) (PD) MCU_PE3_RXIN0/PIO82 665
122 M_LED AA29 MCU_PD1_ADIN1/PIO74 (PD)
122 AB29 MCU_PD2_ADIN2/PIO75 (PD)
MCU_PD3_ADIN3/PIO76 (PD)
C 370 372 122 350 A_DSP_RESET AC29 MCU_PD4_ADIN4/PIO77 (PD) C
350 A_DSP_BOOT_STATUS AD29 MCU_PD5_ADIN5/PIO78 (PD)
791 122 S_CI_VCC_EN R31 MCU_PE1_RXD0/PIO80 (PD) (PD) MCU_PE0_TXD0/PIO79 R32 A_DSP_BUS_EN 350
122 M_PIO81 R30 MCU_PE2_SCLK0_CTS0_N/PIO81 (PD)
790 796 122 S_CI_TS_SEL T32
T31 MCU_PE5_RXD1/PIO84 (PD,OD) (PD,OD) MCU_PE4_TXD1/PIO83 T33 S_CI_CARD_EN 122 793 795
MCU_PE6_SCLK1_CTS1_N/PIO85 (PD,OD)
605 V_MONI_MUTE U31 MCU_PF5_SI1_SCL1/PIO87 (PD) (PD) MCU_PF4_SO1_SDA1/PIO86 U32 R_DEMO_RST 750 122 760 765 770
753 R_TV_SYNC T34 MCU_PF6_SCK1/PIO88 (PD)
630 M_MAINSYNC V30 MCU_PG0_SDA0/PIO89 (PD)
150 161 122 M_GRESET U30 MCU_PG1_SCL0/PIO90 (PD)
N32 MCU_PH0_TB0IN0/EBADD9 (-) Open
- -(-) MCU_PH2_TB0OUT/EBADD11 N30
N31 MCU_PH1_TB0IN1/EBADD10 (-) When
-
P32 MCU_PH3_TB1IN0/EBADD12 (-) Unused -(-) MCU_PH5_TB1OUT/EBADD14
- P30
P31 MCU_PH4_TB1IN1/EBADD13 (-)-
D 122 650 B_FRC_RESET M33 J30 D
M32 MCU_PJ0_INT0/PIO91 (PD) PD When Unused (-) MCU_PK0_CEC K30 M_BL_ONOFF 706
MCU_PJ1_INT1/PIO92 (PD) (PD) MCU_PK1_ALARM_N/PIO94
706 M_PANEL_PWR M31
M30 MCU_PJ2_INT2/PIO93 (PD)
L32 MCU_PJ3_INT3/EBADD26 (-) Open When unused
L31 MCU_PJ4_INT4/EBADD25 (-) Open When unused
L30 MCU_PJ5_INT5/EBADD24 (-) Open When unused
K31 MCU_PJ6_INT6/EBADD23 (-) Open When unused
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