Service Manuals, User Guides, Schematic Diagrams or docs for : TOSHIBA Laptop SATELLITE L755 Toshiba_Satellite_L755
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1 2 3 4 5 6 7 8
PCB STACK UP
LAYER 1 : TOP BLB Block Diagram 01
LAYER 2 : GND
LAYER 3 : IN1
LAYER 4 : IN2
A LAYER 5 : VCC A
LAYER 6 : BOT
USB-11
intel INT_LVDS
LCD/CCD Con. P15
LVDS Port-A
DDRIII-SODIMM1
DDRIII-SODIMM2
Graphics Interfaces
DDR SYSTEM MEMORY
P12,13
INT_CRT CRT Con.
Sandy Bridge P15
Dual Channel DDR III
1066/1333 MHZ
INT_HDMI HDMI
rPGA 989 Level Shift HDMI HDMI Con.
(37.5mm X 37.5mm) Port-B P14
P14
FDI DMI
P2~P5
SATA - HDD
P18 DMI(x4)
PCIE-2 USB 3.0 (BTO)
B B
FDI DMI
SATA - ODD P17
P18
SATA 0
intel
SATA 4 SATA
POWER SYSTEM
PCIE-3 ISL88731CHRTZ-T P.25
USB-1 USB 2.0 (Port0~13) USB-3 3G ISL95835HRTZ-T P.30
USB Con. (BTO) USB RT8207LGQW P.27
P16
P17 CougarPoint RT8240BGQW P.28
PCI-Express
Cardreader USB-4 PCI-E G9661-25ADJF12U P.31
RTC PM6686TR P.26
P21 ISL95870AHRUZ-T P.29
USB-5
SIM Card BATTERY mBGA 989
P16 (25mm X 25mm) PCIE-6
P7 WLAN
Cardreader Con. USB-8 Azalia USB-13 +VCC_CORE
USB Con. HDA P16
3 IN 1 P21
P23 P6~P11
LPC
C
+1.5V C
USB Con. USB-9
+1.5VSUS
P23
PCIE-7 Giga/10/100 Lan +VTT
+1.05V
P20
+1.8V
LPC +3VPCU
+3V_S5
+3V
+5VPCU
Audio Codec EC +5V_S5
P19 P22 +5V
+SMDDR_VTERM
Port-B
Port-A
+SMDDR_VREF
+VGPU_CORE
FAN K/B Con. HALL Sensor SPI Flash Touch Pad /B Power /B +VAXG
D
MDC Con. MIC JACK HP SPK Con. Con. Con. +VCCSA D
P19 P19 P19 P19 P2 P23 P15 P22 P23 P23
Quanta Computer Inc.
PROJECT : BLB
Size Document Number Rev
F3A
Block Diagram
Date: Friday, December 24, 2010 Sheet 1 of 36
1 2 3 4 5 6 7 8
5 4 3 2 1
[6] DMI_TXN0
Sandy Bridge Processor (DMI,PEG,FDI)
B27
U17A
DMI_RX#[0]
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
J22
J21
H22
PEG_COMP
Sandy Bridge Processor (CLK,MISC,JTAG)
02
[6] DMI_TXN1 B25
DMI_RX#[1]
[6] DMI_TXN2 A25
DMI_RX#[2] U17B
[6] DMI_TXN3 B24 K33 B2A 10/05
DMI_RX#[3] PEG_RX#[0]
M35
PEG_RX#[1]
[6] DMI_TXP0 B28 L34
DMI_RX[0] PEG_RX#[2]
[6] DMI_TXP1 B26 J35
DMI_RX[1] PEG_RX#[3]
DMI
A24 J32 A28 CLK_CPU_BCLKP_R 3 4 CLK_CPU_BCLKP [8]
MISC
CLOCKS
[6] DMI_TXP2 DMI_RX[2] PEG_RX#[4] BCLK
[6] DMI_TXP3 B23 H34 [7] H_SNB_IVB# C26 A27 CLK_CPU_BCLKN_R 1 2 CLK_CPU_BCLKN [8]
DMI_RX[3] PEG_RX#[5] PROC_SELECT# BCLK# R440 0X2
H31
PEG_RX#[6]
[6] DMI_RXN0 G21 G33
DMI_TX#[0] PEG_RX#[7] SKTOCC#
[6] DMI_RXN1 E22 G30 TP5 AN34
D DMI_TX#[1] PEG_RX#[8] SKTOCC# D
[6] DMI_RXN2 F21 F35 A16 CLK_DPLL_SSCLKP_R R443 1K_4
DMI_TX#[2] PEG_RX#[9] DPLL_REF_CLK
[6] DMI_RXN3 D21 E34 A15 CLK_DPLL_SSCLKN_R +VTT
DMI_TX#[3] PEG_RX#[10] DPLL_REF_CLK# R444 1K_4
E32
PEG_RX#[11]
[6] DMI_RXP0 G22 D33
DMI_TX[0] PEG_RX#[12] TP_CATERR#
[6] DMI_RXP1 D22 D31 TP3 AL33
DMI_TX[1] PEG_RX#[13] CATERR#
PCI EXPRESS* - GRAPHICS
[6] DMI_RXP2 F20 B33
DMI_TX[2] PEG_RX#[14]
C21 C32 B2A 10/05
THERMAL
[6] DMI_RXP3 DMI_TX[3] PEG_RX#[15]
J33 AN33 R8 CPU_DRAMRST#
PEG_RX[0] [22] EC_PECI PECI SM_DRAMRST#
L35 B2A 10/05
DDR3
MISC
PEG_RX[1]
K34
PEG_RX[2]
[6] FDI_TXN0 A21 H35
FDI0_TX#[0] PEG_RX[3] R58 56_4 H_PROCHOT#_R SM_RCOMP_0 R452 140/F_4
[6] FDI_TXN1 H19 H32 [22,30] H_PROCHOT# AL32 AK1
FDI0_TX#[1] PEG_RX[4] PROCHOT# SM_RCOMP[0] SM_RCOMP_1 R441 25.5/F_4
[6] FDI_TXN2 E19 G34 A5
FDI0_TX#[2] PEG_RX[5] SM_RCOMP[1]
Intel(R) FDI
F18 G31 A4 SM_RCOMP_2 R442 200/F_4
[6] FDI_TXN3 FDI0_TX#[3] PEG_RX[6] SM_RCOMP[2]
[6] FDI_TXN4 B21 F33
FDI1_TX#[0] PEG_RX[7] PM_THRMTRIP#_R AN32
[6] FDI_TXN5 C20 F30
FDI1_TX#[1] PEG_RX[8] THERMTRIP#
[6] FDI_TXN6 D18 E35
FDI1_TX#[2] PEG_RX[9]
[6] FDI_TXN7 E17 E33
FDI1_TX#[3] PEG_RX[10]
F32
PEG_RX[11]
D34 B2A 10/05
PEG_RX[12]
[6] FDI_TXP0 A22 E31 AP29 XDP_PRDY#_R TP80
FDI0_TX[0] PEG_RX[13] PM_SYNC_R PRDY#
[6] FDI_TXP1 G19 C33 [6] PM_SYNC R49 0_4 AP27 XDP_PREQ#_R TP81
FDI0_TX[1] PEG_RX[14] PREQ#
[6] FDI_TXP2 E20 B32
FDI0_TX[2] PEG_RX[15]
G18 AR26 XDP_TCLK_R
PWR MANAGEMENT
[6] FDI_TXP3 FDI0_TX[3] TCK
JTAG & BPM
[6] FDI_TXP4 B20 M29 AR27 XDP_TMS_R
FDI1_TX[0] PEG_TX#[0] TMS
[6] FDI_TXP5 C19 M32 AM34 AP30 XDP_TRST#_R
FDI1_TX[1] PEG_TX#[1] PM_SYNC TRST#
[6] FDI_TXP6 D19 M31
FDI1_TX[2] PEG_TX#[2]
[6] FDI_TXP7 F17 L32 When XDP connect be use AR28 XDP_TDI_R
FDI1_TX[3] PEG_TX#[3] TDI
L29 AP26 XDP_TDO_R
J18
PEG_TX#[4]
K31
must change to 1K AP33
TDO
[6] FDI_FSYNC0 FDI0_FSYNC PEG_TX#[5] UNCOREPWRGOOD
[6] FDI_FSYNC1 J17 K28 B2A 10/05
FDI1_FSYNC PEG_TX#[6] R63 0_4 H_PWRGOOD_R
J30 [9] H_PWRGOOD
PEG_TX#[7] XDP_DBR#_R R917 0_4
[6] FDI_INT H20 J28 AL35 XDP_DBRST# [6]
FDI_INT PEG_TX#[8] DBR#
H29 V8
PEG_TX#[9] R61 10K_4 SM_DRAMPWROK
[6] FDI_LSYNC0 J19 G27
FDI0_LSYNC PEG_TX#[10]
[6] FDI_LSYNC1 H17 E29 C945 0.1U/10V_4X AT28 XDP_OBS0_R TP82
FDI1_LSYNC PEG_TX#[11] BPM#[0]
F27 AR29 XDP_OBS1_R TP83
PEG_TX#[12] PM_DRAM_PWRGD_R BPM#[1]
D28 AR30 XDP_OBS2_R TP84
PEG_TX#[13] BPM#[2]
C
B2A 10/05 F26 AR33 AT30 XDP_OBS3_R TP85
C
PEG_TX#[14] RESET# BPM#[3]
E25 AP32 XDP_OBS4_R TP86
PEG_TX#[15] CPU_PLTRST# CPU_PLTRST#_R BPM#[4]
A18 R67 *43_4 AR31 XDP_OBS5_R TP87
eDP_COMP eDP_COMPIO BPM#[5]
A17 M28 AT31 XDP_OBS6_R TP88 B2A 10/05
INT_eDP_HPD_Q eDP_ICOMPO PEG_TX[0] BPM#[6]
TP89 B16 M33 +VTT R66 *75/F_4 AR32 XDP_OBS7_R TP90
eDP_HPD PEG_TX[1] BPM#[7]
M30
PEG_TX[2]
L31
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