Service Manuals, User Guides, Schematic Diagrams or docs for : Tektronix 7d11_svc_sm
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download 7d11_svc_sm documenatation <<
Text preview - extract from the document
xrm~l
71311 Service
TABLE OF CONTENTS
SECTION 1 OPERATING INFORMATION Page
71311 FEATURES 1-1
PRELIMINARY INFORMATION 1-1
Installation 1-1
Display 1-1
CONTROLS AND CONNECTORS 1-3
GENERAL OPERATING INFORMATION 1-3
Signal Connection 1-3
Count Mode 1-4
Trigger Controls 1-4
Triggered Light 1-4
Trigger Coupling 1-4
Trigger Source 1-5
Trigger Slope/Level 1-5
Events Start Trigger 1-5
Delay Time or Events 1-5
Fine Delay 1-5
B Sweep Delay Mode 1-5
OUTPUT SIGNALS 1-6
Front Panel Output Signals 1-6
Output Signals to Mainframe 1-6
OPERATING MODES 1-7
Sweep Delay 1-7
Echo Delay Time Mode 1-7
SECTION 2 THEORY OF OPERATION
INTRODUCTION 2-1
BLOCK DIAGRAM 2-1
Time/Events Trigger 2-1
Phase Lock Loop and Gated Countdown 2-1
Outputs Processing and Events Start Trigger 2-1
Delaying Counter and Display Generator 2-1
Readout Encoding 2-1
7D11 Service
TABLE OF CONTENTS (cont)
SECTION 2 THEORY OF OPERATION (cont) Page
THEORY OF OPERATION 2-2
TRIGGER CIRCUITSO 2-2
Trigger Preamp 2-2
Trigger Generator 2-3
PHASE LOCK LOOP AND GATED COUNTDOWN 2-5
Phase Lock Loop 2-5
Fine Delay 2-6
Gated Countdown 2-6
OUTPUTS PROCESSING AND EVENTS
START TRIGGER 3O 2-9
Time/Events Count Source Gate 2-9
Delayed Trigger Output Flip-Flop 2-9
Delayed Gate Flip-Flop 2-10
2-11
O
Events Start Trigger
DELAYING COUNTER AND DISPLAY GENERATOR 2-11
Voltage to Frequency Converter 2-11
Reversible Counter and Nines Complement Review 2-12
Delaying Counter 2-12
Power-On Initi`alizer 2-12
Reset 2-13
READOUT ENCODING 2-13
POWER DISTRIBUTION AND MAINFRAME
CONNECTOR O6 2-13
D .C . Inverter 2-14
INTRODUCTION TO THE READOUT SYSTEM 2-14
Introduction 2-14
The Readout System 2-14
SECTION 3 MAINTENANCE
INTRODUCTION 3-1
PREVENTIVE MAINTENANCE 3-1
General 3-1
Cleaning 3-1
Lubrication 3-1
Recalibration 3-1
71311 Service
TABLE OF CONTENTS (cont)
SECTION 3 MAINTENANCE (cont) Page
TROUBLESHOOTING 3-1
General 3-1
Troubleshooting Aids 3-1
Troubleshooting Equipment 3-2
Troubleshooting Procedure 3-2
REPLACEMENT PARTS 3-3
Standard Parts 3-3
Transistor and Integrated Circuit Replacement 3-3
Recalibration After Repair 3-3
Special Parts 3-3
Ordering Parts 3-3
Repackaging for Shipment 3-3
SECTION 4 CALIBRATION
Calibration Interval 4-1
Tektronix Field Service 4-1
Using This Procedure 4-1
TEST EQUIPMENT REQUIRED 4-1
General 4-1
Test Equipment Alternatives 4-1
Signal Connections 4-1
CALIBRATION PROCEDURE INTRODUCTION 4-4
Index to Calibration Procedure 4-4
Preliminary Procedure 4-5
DIGITAL READOUT DISPLAY 4-6
TRIGGERING 4-7
EVENTS COUNT MODE 4-11
TIME COUNT MODE 4-14
OUTPUT SIGNALS 4-19
SECTION 5 ELECTRICAL PARTS LIST
SECTION 6 DIAGRAMS
SECTION 7 MECHANICAL PARTS LIST
CHANGE INFORMATION
REV . B, FEB . 1977
Fig. 1-1 . 71311 Digital Delay.
Section 1-71311 Service
OPERATING INFORMATION
71311 FEATURES a vertical amplifier unit . The 71311 must be operated in the
A Horizontal compartment to control the delay mode of a
The 71311 Digital Delay plug-in unit is designed for use time-base unit in the B Horizontal compartment. Operation
with Tektronix 7000-series Oscilloscope mainframes in a vertical compartment is necessary to view the Delay
equipped with a readout system . The 71311 uses the Interval Pedestal without the use of external cables.
readout system to display the selected delay count on the
CRT. A delayed trigger output is generated by counting
time or events . Digital delay time to one second is read out
To install the 71311 into a plug-in compartment, push
in 100-nanosecond increments . Additional analog delay
the unit in until it is seated flush against the front panel of
time from zero to 100 nanoseconds selected from a
the mainframe. To remove, pull the release latch to
calibrated front-panel dial provides added resolution . An
disengage the 71311 . Continue to pull the release latch to
"echo" time-delay mode provides a divide-by-two scaler to
remove the unit from the mainframe.
read out the "one-way trip" time, up to,two seconds, for
radar ranging and TDR applications . Delay time accuracy is
controlled by an internal crystal oscillator ; greater accuracy
can be obtained by the use of an external one-megahertz
standard . In the Count by Events mode, the CRT readout
displays the integer number of events from one to 107 Display
events at count rates up to 50 megahertz. The 71311 readout display is presented on the CRT of
the mainframe, along with information encoded by the
other plug-in units. Digital delay time (in milliseconds) is
The 71311 can be used to delay a 7B-series time-base unit displayed in five to eight digits . The + symbol to the right
in either a runs-after or triggerable-after delay time mode . of the digital display reminds the operator to add any
Other 71311 features include on-screen display of delay analog delay time selected by the FINE DELAY (ns) dial to
interval by vertical signal or display blanking, trigger the delay time . The number of events being counted is
pickoff from vertical amplifier unit, and blanking of the presented in a seven to eight digit display .
two leading zeros (count by time mode only) .
The 71311 readout display appears on the CRT in a
location corresponding to the plug-in compartment used .
PRELIMINARY INFORMATION
The delay time or number of events will be displayed in the
top division of the CRT graticule. The delay-time measure-
Installation
ment unit (ms) will be displayed in the bottom division . It
The 71311 is designed to operate in any plug-in compart- is not necessary to select the 71311 with the mainframe
ment of Tektronix 7000-series mainframes . However, cer- Vertical or Horizontal Mode switches to view the digital
tain modes of operation require the 71311 to be installed in display . In order to view the Delay Interval Pedestal
a specific compartment. The unit must be operated in a waveform, selection with the Vertical Mode switch is
horizontal compartment to trigger from a signal applied to required .
REV . B, OCT . 1974
Operating Information-7D11 Service
Fig. 1-2. 7D11 front-panel controls and connectors.
Operating Information-71311 Service
CONTROLS AND CONNECTORS DLY'D TRIG OUT
BNC connector for Delayed Trigger output
The major controls and connectors for operation of the signal .
71311 are located on the front panel of the unit . Two
controls located inside the unit for auxiliary functions are
described in the General Operating Information section. EXT 1 MHz IN or EVENTS START TRIG IN
The front-panel controls and connectors are identified in BNC connector for input of external 1 MHz
Fig . 1-2 ; their functions are as follows:
time=reference signal or input of Events Start
Trigger input signal . Connector function is deter-
mined by setting of COUNT MODE switch .
COUNT MODE Switch
Selects mode of operation and clock-signal
source for Time count mode . DLY INTERVAL OUT
BNC connector for Delay Interval output signal .
B SWEEP DELAY MODE Switch
Selects the delay mode logic for time-base unit in
14 EXT TRIG IN
B Horizontal compartment of mainframe.
BNC connector for external input to Trigger
circuit (selected by SOURCE switch in the
TRIGGER SLOPE/LEVEL Controls external positions) .
Select slope and amplitude point of input signal
where the delay is initiated.
GENERAL OPERATING INFORMATION
TRIG'D Indicator Signal Connection
Lights when a trigger is produced . In general, probes offer the most convenient means of
connecting signals to the 71311 external trigger inputs .
Tektronix probes are shielded to prevent pickup of electro-
F5 I COUPLING Switch static interference . A 10X attenuation probe offers a high
Selects the method of coupling the input signal input impedance and allows the circuit under test to
to the Trigger circuit. perform very close to normal operating conditions . Also, a
10X probe attenuates the input signal ten times.
6 SOURCE Switch
Selects Trigger input signal source . Tektronix probes are designed to monitor the signal
source with minimum circuit loading . The use of a probe
will, however, limit the maximum trigger frequency range.
EVENTS START TRIGGER SLOPE/LEVEL To obtain maximum trigger bandwidth when using probes,
Controls select a probe capable of compensating the input capaci-
tance; observe the grounding considerations given in the
Select slope and amplitude point of input signal
probe manual . The probe-to-connector adapters and the
where the Events Start count is initiated .
bayonet-ground tip provide the best frequency response .
8 DELAY TIME OR EVENTS Control In high-frequency applications, requiring maximum over-
Selects delay time or number of events counted. all bandwidth, use a coaxial cable terminated at both ends
Direction of rotation selects increase or decrease in the characteristic impedance of the cable. To maintain
in delay time or number of events . the high-frequency characteristics of the applied signal, use
high-quality low-loss cable. Resistive coaxial attenuators
can be used to minimize reflection if the applied signal has
9 RESET suitable amplitude.
Resets the DELAY TIME or EVENTS to
0000001 . High-level, low-frequency signals can be connected
directly to the external trigger inputs with short, unshielded
leads. When this method is used, establish a common
10 FINE DELAY (ns) Dial ground between the 71311 and the associated equipment.
Selects analog delay time added to digital delay The common ground provided by the line cords is usually
time selected by DELAY TIME OR EVENTS inadequate. If interference is excessive with unshielded
control . leads, use a coaxial cable or probe .
Operating Information-7D11 Service
A signal can also be routed to the 7D11 through an Triggered Light
amplifier unit via the internal trigger circuitry of the
mainframe (7D11 installed in a horizontal compartment) . The TRIG'D light provides a convenient indication of
This method of signal connection minimizes circuit loading, the Trigger circuit condition . If the TRIGGER controls are
especially when triggering a time-base unit in parallel with correctly set and an adequate signal is applied, the TRIG'D
the 7D11 . light is on . If the TRIG'D light is off, no delay interval is
started . The cause might be an incorrectly set TRIGGER
control, low signal amplitude, or a signal repetition rate
NOTE
outside the usable frequency range. This feature can be
used as a general indication of correct triggering when there
Only external signals can be used with the Events is no display on the CRT. The Delay Interval Pedestal and
Start Trigger. Z-Axis Blanking displays also aid in obtaining correct
TRIGGER control settings . See the discussion of these
The front-panel output signals, DLY'D TRIG OUT and features under Output Signals to Mainframe for further
DLY INTERVAL OUT, should be connected to other information .
equipment with 50-ohm coaxial cables . The cables should
be terminated in 50 ohms to maintain the rise and falltime NO TE
characteristics of these signals.
When the 7D 11 is used in the EVENTS count mode,
Count Mode the EVENTS START TRIGGER affects the output
of the Trigger circuit but has no effect on the
General. Two basic count modes, Time and Events, can TRIG'D light.
be performed by the 7D11, as selected by the COUNT
MODE switch . The delay interval in both modes is selected
by the DELAY TIME OR EVENTS control and is read out Trigger Coupling
on the CRT. The TRIGGER pushbuttons located below the
COUPLING title select the method in which the input
TIME INT CLOCK . The 7D11 counts precise incre- signal is connected to the Trigger circuit . Each position
permits selection or rejection of various frequency compo-
ments of time after the receipt of a trigger. The TRIGGER
controls select and condition the signal to start the time nents of the signal used to trigger the delay start.
delay . Accuracy in this mode is determined by an internal,
AC . In this position of the COUPLING switch, the DC
crystal-controlled oscillator .
component of the input signal is blocked . Signals with
low-frequency components below about 30 hertz are
TIME EXT 1 MHz. This count mode is the same as attenuated . In general, AC COUPLING can be used for
TIME INT CLOCK except the accuracy is derived from an most applications . However, if the signal contains unwanted
external, one-megahertz standard . frequency components or if the delay is to be triggered at a
low repetition rate or DC level, one of the other switch
positions will provide better results.
EVENTS . The 7D11 counts events, periodic or aperi-
odic, at count rates to 50 megahertz . The EVENTS START The triggering point in the AC position depends upon
TRIGGER provides a means of discriminating between the the average voltage level of the input signal . If the input
event that starts the delay and the events to be counted . signal occurs randomly, the average voltage level will vary,
The events to be counted are selected and conditioned by causing the triggering point to vary also . This shift of the
the TRIGGER controls . triggering point may be enough so it is impossible to
maintain a stable delay start; in such cases, use DC
coupling .
Trigger Controls AC LF REJ. In this position, DC is rejected and
low-frequency input signals below about 30 kilohertz are
The input signal may have a wide variety of shapes and attenuated . Therefore, the delay is triggered only by the
amplitudes, many of which are unsuitable as delay-initiating higher-frequency components of the input signal . The AC
triggers. For this reason, these signals are first applied to a LF REJ position is particularly useful for providing stable
trigger circuit where they are converted to pulses of triggering if the input signal contains line-frequency compo-
uniform amplitude and shape. This makes it possible to nents.
start the delay with a pulse that has a constant size,
eliminating variations of the delay circuit operation caused AC HF REJ. This COUPLING switch position passes all
by changing input signals. The TRIGGER controls provide low-frequency signals between about 30 hertz and 50
a means to select the signal source, filter unwanted kilohertz. DC is rejected and signals above 50 kilohertz are
frequencies, and start the delay at any voltage level on attenuated . This position is useful to trigger the delay from
either slope of the waveform . the low-frequency components of a COMDlex waveform .
Operating Information-71311 Service
DC . The DC position can be used to provide stable Events Start Trigger
triggering from low-frequency or low-repetition-rate signals
which would be attenuated in other modes. It can also be The Events Start Trigger is used in the EVENTS count
used to trigger the delay when the input signal reaches a DC mode to differentiate between the event that starts the
level selected by the setting of the SLOPE/LEVEL control . delay and the events being counted .
When triggering from the internal source, the setting of the
vertical unit position control(s) affects the DC triggering The EVENTS START TRIG IN connector provides the
point. input to the events-start signal . The EVENTS START
TRIGGER SLOPE and LEVEL controls select the ampli-
tude point and slope on the input signal where the delay is
Trigger Source triggered.
The TRIGGER pushbuttons located below the SOURCE
title select the source of the signal connected to the Trigger Delay Time or Events
circuit .
The DELAY TIME OR EVENTS control selects the
digital delay time in the TIME count mode, and the number
INT. In this position, the input signal is derived from
of events counted in the EVENTS count mode . The delay
the associated vertical unit . Therefore, the 71311 must be
time in milliseconds, or integer number of events, selected
installed in a horizontal compartment to use the internal
is displayed on the CRT readout.
source . Further selection of the internal signal may be
provided by the vertical unit and mainframe; see the This control is a spring-return-to-center control that
instruction manuals for these instruments for further increases or decreases the count at which a delayed pulse
information . will occur. The direction of rotation determines whether
the count is increased or decreased. The rate at which the
LINE . In this SOURCE switch position, a sample of the count increments is determined by the magnitude of
power-line voltage from the mainframe is connected to the rotation . After either extreme of the range is reached, the
Trigger circuit. Line triggering is useful when the input next count starts from the other end of the range. For
signal is time related (multiple or submultiple) to the line example, if the delay time is increased above 1000 .0000 ms
frequency . It is also useful for providing stable triggering (one second), the count will go to 0.0001 ms. Conversely, if
from a line-frequency component in a complex waveform . the delay time is decreased past 0.0001 ms, the count will
go to 1000.0000 ms .
EXT. A signal connected to the EXT TRIG IN con- Fine Delay
nector can be used to trigger the delay in the EXT position
of the SOURCE switch . An external signal can be used to The FINE DELAY (ns) dial selects analog delay time
provide a trigger when the internal signal amplitude is too from zero to 100 nanoseconds in the TIME count mode .
low. This one-turn control provides added resolution to the
digital delay time selected by the DELAY TIME OR
EVENTS control . The delay time selected by the FINE
EXT= 10 . Operation in this position is the same as DELAY (ns) dial is read from the calibrated knob as the
described for EXT except the external signal is attenuated analog delay time is not read out on the CRT. Each minor
10 times. Attenuation of high-amplitude signals is desirable division on the dial represents two nanoseconds.
to extend the range of the LEVEL control.
B Sweep Delay Mode
Trigger Slope/Level The B SWEEP DELAY MODE switch permits the 71311,
under specific conditions, to select the delay mode of a
The TRIGGER SLOPE/LEVEL controls determine the
compatible time-base unit . To use this feature, the 71311 is
slope and voltage level of the input signal where the Trigger
installed in the A Horizontal compartment and the time-
circuit responds . Generally, the best point on a waveform
base in the B Horizontal compartment of a four-plug-in
for triggering the delay is where the slope is steep, and
mainframe. With this arrangement, the time-base unit can
therefore usually free of noise. Assuming a sine-wave input
be controlled through the mainframe interface. Some dual
waveform, the steepest slope occurs at the zero-crossing
time-base units are not compatible with this feature; see the
point. This is the point selected for triggering when the
time-base unit instruction manual for further information .
LEVEL control is set to 0 (center) . A more positive or
negative point on the waveform is selected as the LEVEL
INDEPENDENT. The 71311 and the time-base unit
control is rotated clockwise or counterclockwise respec-
operate independently .
tively from 0 (toward + or - symbols on panel) .
B STARTS AFTER DELAY. The time-base unit pro-
Before setting the TRIGGER LEVEL, the desired duces a sweep immediately following the selected delay
SLOPE, MODE, COUPLING, and SOURCE should be interval . This provides the same mode of operation as
selected . Then adjust the LEVEL control so the delay starts triggering the time-base unit with the delayed trigger
from the desired point. output.
Operating Information-7D11 Service
B TRIGGERABLE AFTER DELAY . The time-base unit 7D11 is set for a 0 .0038-millisecond delay time after
produces a sweep after the first trigger pulse is received triggering on the ten-microsecond markers . The resultant
following the selected delay interval . This mode of opera- Delay Interval and Delayed Trigger outputs are shown in
tion provides a stable display of a signal having time jitter . Fig . 1-3(B) and (C), respectively .
Precision time measurements cannot be made in this mode
because the actual delay time is only partially dependent on
the delay interval of the 7D 11 . Output Signals to Mainframe
General . Signal outputs are provided to the mainframe
via the interface connector . The following discussion
OUTPUT SIGNALS
describes these signals and the operating conditions neces-
sary for their use .
Front-Panel Output Signals
General . The Delay Interval and Delayed Trigger out-
puts are available at the front-panel IDLY INTERVAL OUT Delay-Interval Pedestal . This output provides an on-
and DLY'D TRIG OUT connectors respectively . These screen display of the approximate delay interval . To view
outputs can be used to control other equipment during or the pedestal display, the 7D11 must be installed in a
immediately following the delay interval . To maintain the vertical plug-in compartment and be selected by the
rise and failtime characteristics of these signals, connection mainframe Vertical Mode switch . The position of this
to other equipment should be made with 50-ohm coaxial display is fixed near the vertical center of the graticule area .
cable ; the output of the cable should be terminated in 50 The Delay-Interval Pedestal display is shown in Fig . 1-4(A) .
ohms . The input signal, shown in Fig . 1-4(B), is comprised of one-
and ten-microsecond time markers . The 7D11 is set to
trigger on the ten-microsecond markers, and to generate a
IDLY INTERVAL OUT. This output is a positive-going, 0 .0038-millisecond delay time .
rectangular waveform coincident with the generated delay
interval . In the time mode, the IDLY INTERVAL OUT is
approximately 20-30 nanoseconds shorter than the indi-
cated delay time because of internal propagation delays and
trigger recognition time . In the event mode, the IDLY
INTERVAL OUT is within 30 nanoseconds of actual delay,
usually 10 nanoseconds .
DLY'D TRIG OUT . This signal is generated as a
positive-going rectangular pulse coincident with the end of
the delay interval .
The front-panel output signals are shown in Fig . 1-3,
along with the input signal . The input signal, Fig . 1-3(A), is
comprised of one- and ten-microsecond time markers . The
Fig . 1-4 . Waveform display of : (A) Delay Interval Pedestal ; (B)
input signal .
Delayed Trigger . The Delayed Trigger output provides
an internal Delayed Trigger source for a time-base unit . A
time-base unit can be triggered from the Delay Trigger
when the 7D11 is in a vertical compartment . To use this
output, the 7D11 must be selected by the appropriate
trigger source switch (mainframe) .
Z-Axis Blanking . Z-axis blanking provides an on-screen
display of the approximate delay interval . This is accom-
plished by blanking out the CRT display during the delay
interval . Z-axis blanking can be obtained with the 7D11
installed in any plug-in compartment . The Z-axis blanking
display is selected by a slide switch located inside the unit
Fig . 1-3 . Display showing time relationship of : (A) Input signal to
the front panel ; (B) Delay Interval ; and (C) Delayed Trigger outputs . (on the left side ; see Fig . 1-5) .
Operating Information- 7D11 Service
NO TE
The logic levels provided to the 7D11 from the
mainframe are designed to control a time-base unit
delaying sweep . For this reason, the 7D11 might
become locked out (no output) when the setting of
either the B-Sweep unit Time/Division switch or the
B SWEEP DELAY MODE switch is changed. If this
occurs, a delayed sweep will not be produced. To
reset the 7D11, set the B SWEEP DELAY MODE
switch first to INDEPENDENT, then select the
desired delay mode.
Internal Trigger . The sweep produced by a time-base
unit in a horizontal compartment can be internally trig-
gered from a 7D11 in a vertical compartment . To use this
sweep delay mode, the 7D11 must be selected by the
mainframe trigger source switch . Delaying a time-base
Fig . 1-5 . Location of Z-Axis Blanking Display switch (on left side sweep from the internal source can be used with the units
of instrument) . The switch position towards the rear of the unit installed in either a three- or four-plug-in mainframe .
selects Z-axis blanking .
External Trigger Source . A sweep can be delayed by
NO TE external triggering from the DLY'D TRIG OUT connector .
This method can be used with any triggered sweep .
At faster sweep speeds (100 nsldiv or faster) care
must be taken when interpreting CRT display because Echo Delay Time Mode
relative propagation delays through the 7D11 and
vertical amplifier plug-ins are not the same. This The Echo delay time mode provides a CRT readout of
appears as a relative time shift between delay interval the "one-way-trip" time, or one-half of the generated delay
pedestal or Z-axis blanking generated by the 7D 11 time . This mode of operation is selected for use by an
and the signal(s) viewed through a vertical amplifier internal switch (on left side of unit, see Fig . 1-6) . In the
on the CRT. Changing the TRIG SOURCE between Echo mode, the delay time is selected by the DELAY TIME
INT and EXT or EXT _ 10 will vary this apparent OR EVENTS control in 200-nanosecond increments . An
time shift due to differences in propagation delays of insertion delay of about 160 nanoseconds in this mode
the signal path . requires adding analog delay time to the first delay
increment to obtain a 200-nanosecond delay interval . This
can be accomplished by displaying the DELAY INTERVAL
OPERATING MODES OUT and setting the FINE DELAY dial for a total delay
interval of 200 nanoseconds as measured on the graticule .
Sweep Delay
The 7D11 can be used to delay the start of a sweep for a
selected time interval following the receipt of a trigger .
Low-jitter sweep delay can be used for accurate time, jitter,
and stability measurements . Sweep delay can also be used
to select a portion of a complex signal for display . A sweep
is delayed by triggering the sweep from the Delayed Trigger
output of the 7D11, rather than from the signal to be
displayed . Several methods of coupling the Delayed Trigger
to the sweep are possible, depending on the application .
These methods are described in the following discussions .
B Sweep Delay Mode Switch . The sweep produced by a
time-base unit can be controlled and delayed by a 7D11 via
the mainframe interface and the B SWEEP DELAY MODE
switch . To use this mode of sweep delay, the 7D 11 must be
installed in the A Horizontal compartment and the time-
base unit in the B Horizontal compartment of a four-plug-in Fig . 1-6 . Location of Normal-Echo Delay Time Mode switch (on
mainframe . For further information, see B Sweep Delay left side of unit) . Set the switch towards the front of the unit to
Mode . select Normal Mode .
Section 2-7D11 Service
THEORY OF OPERATION
INTRODUCTION Phase Lock Loop and Gated Countdown
The Phase Lock Loop and Gated Countdown block
consists of two main sections . One section is the phase lock
This section provides a general, block diagram descrip-
loop that supplies a stable 500-megahertz clock, phase
tion of the 7D11 . This is followed by the theory of
locked to an internal five-megahertz crystal or to an
operation which is keyed to the schematic diagrams of the
external one-megahertz reference. The second section con-
circuits described. If more information is desired on
sists of the fine delay and gated countdown circuits . When a
commonly used circuits, refer to the following textbook :
trigger is received from the trigger section, it is routed
through the Fine Time Delay Multi-stage where it is delayed
an additional amount, determined by the front panel
Jacob Millman and Herbert Taub-, "Pulse, Digital, and control, to the Time Count Switch . Once the Time Count
Switching Waveforms", McGraw-Hill, New York, 1965 . Switch is opened, it allows the 500-megahertz clock to be
divided down to 10 megahertz. This 10-megahertz signal is
then presented to the Time/Events Count Source Gate in
the Outputs processing and Events Start Trigger section.
Following the theory of operation is a brief discussion of Outputs Processing and Events Start Trigger
the readout system used in Tektronix 7000-series Oscillo-
The Outputs Processing and Events Start Trigger section
scopes . If more information is required on the readout
performs several internal and reset functions in addition to
system, refer to the instruction manual for the oscilloscope .
providing the various outputs of the 7D11 . This circuit
provides B sweep delay, Z-axis intensification during the
delay interval, the delay interval out pedestal, and the
delayed trigger output . This circuit also contains the Events
Start Trigger, which allows counting of events trigger in the
delay by events mode .
BLOCK DIAGRAM
Delaying Counter and Display Generator
The Delaying Counter and Display Generator section
The block diagram is divided into the following five provides the circuitry for setting up the delay by time or
main sections , Time/Events Trigger, Phase Lock Loop and
delay by events count. The delay is set up as the nines
Gated Countdown, Outputs Processing and Events Start
complement of the delay count in the Reversible Counter
Trigger, Delaying Counter and Display Generator, and
by the DELAY TIME OR EVENTS CONTROL and is
Readout Encoding . counted by the Delaying Counter. The Delaying Counter
counts time from 100 nanoseconds to one second or counts
events to 10,000,000 . When the preset delay count is
completed (the count signal to the Delaying Counter comes
from the Time/Events Count Source Gate on block 3), the
Nines Arm Gate activates the Output Release Gate on block
3. This simultaneously ends the DLY INTERVAL OUT and
activates the DLY'D TRIGGER OUT .
Time/Events Trigger
The Time/Events Trigger circuit processes the trigger
Readout Encoding
signal for starting the delay by time count through the
Phase Lock Loop and Gated Countdown circuit when in The delay time or events setting is encoded by the
the delay by time mode . In the delay by events mode the Readout Encoding section . These circuits provide necessary
trigger circuit provides the actual count signal, derived from information to the readout system in the associated
the signal selected by the SOURCE and COUPLING mainframe to allow the delay time or events count to be
switches . displayed on the CRT .
REV . B, FEB . 1977
Theory of Operation-7D11 Service
THEORY OF OPERATION selecting EXT - 10 . R6 and R7 (paralleled by R30) form a
10 :1 attenuator .
The following theory of operation discussion is refer-
enced to the schematic diagrams in the diagram section of The input impedance for the trigger input is one
this manual . Each main topic heading is followed by the megohm, consisting primarily of R 12 and R30. This resistor
number of the schematic to which it applies. pair also causes a 2X attenuation of the input signal as seen
at the gate of Q32 A and B. C24 serves to compensate the
input stage and C10 compensates the 10X attenuator .
TRIGGER CIRCUITS
The trigger circuit consists of two main sections, the CR27 and CR28 protect Q32 from excessive input signal
trigger preamp and the trigger generator. by clamping the gate if the signal at the input connector
exceeds approximately plus or minus 2.5 volts. The signal
at the source of Q32 is coupled through emitter follower
Trigger Prearnp Q37 to the base of Q41 . Q41 is another emitter follower,
which drives U60. The signal at pin 7 of U60 is terminated
The trigger preamp serves to select trigger source and in approximately 50 ohms by R46 to preserve the
coupling for the trigger generator . This circuit may be high-frequency characteristics.
considered as consisting of the following four elements :
Trigger Source Switching, U60; External Trigger Preamp or
external input amplifier, Q32, 037, and Q41 ; Balanced-to- R49 sets the DC level at pin 10 of U60, which is the
Single-Ended Converter, Q71, Q75, and Q78; and Trigger negative side of the external trigger differential input. This
Coupling, 082, Q84, and Q86. serves to match the DC balance of the external trigger input
of U60 to that of the internal trigger input .
Trigger Source Switching. U60 receives internal trigger
inputs at pins 2 and 15 and external trigger signals at pin 7. Balanced-To-Single-Ended Converter. Q71, Q78, and
U60 determines which input signal is selected by means of a Q75 convert the balanced (push-pull) output of U60 to a
digital signal (voltage level) at pin 4 . A LO on pin 4 single-ended signal at the emitter of Q75 .
activates pins 2 and 15 for internal triggering, while a HI on
pin 4 switches U60 to activate pins 7 and 10 for external
triggering . The trigger signal through U60 causes a decrease in
current into pin 12 from R77 and R78 and an increase in
current into pin 13 from R71 . This would normally cause
To further examine U60, assume that pin 4 is low, the voltage at pin 12 to swing in a positive direction, while
activating pins 2 and 15 for internal triggering . This input is pin 13 goes in a negative direction. However, the current
a relatively high impedance differential configuration . Pin through R77 and R78 actually increases due to the
15 receives the positive-going trigger signal and pin 2 is the feedback via R79 and Q78, causing the voltage at pin 12 to
negative-going input . The inputs are biased at the center of swing negative along with pin 13 . Q78 is connected as a
their dynamic range and signal limiting in the trigger diode and is enclosed in the same heat-sink with Q71,
pickoff circuitry (in the indicator oscilloscope) ensures that providing good DC stability .
the inputs will not be driven into cutoff or saturation . R55
and R57 terminate the internal trigger signal from the
indicator oscilloscope . The analog current source for
Trigger Coupling . When DC coupling is selected by the
internal triggering is through pins 1 and 16 .
front panel COUPLING switch, Q86 is turned on by the
+15 volt supply through R92, S95, and R86 to its base . The
triggering signal is then coupled through R80 and Q86 to
The switch output current appears at pins 12 and 13 . A
the base of Q100 .
positive-going signal at pin 15 will cause an increase in
current into pin 13 and out through pin 16, R66, and R69.
Simultaneously, the negative-going signal at pin 2 causes a
decrease in current into pin 12 and out through pin 1, R68, Q84 is turned on when AC coupling is selected . The
triggering signal then passes through Q84 and C87 to the
and R69 . The net result is that the total current through
base of Q100 . For AC LF REJ coupling, Q84 is off and the
pins 12 and 13 and through R69 remains constant .
triggering signal is coupled through C88 and C87 to
attenuate low frequency signals.
External Trigger Preamp . This circuit includes Q32, 037
and Q41 . The SOURCE switch (S5) at the input selects
internal, external, or line signals for triggering . The external For AC H F REJ coupling, both Q84 and Q82 are turned
trigger signal may be attenuated to one-tenth amplitude by on . The high-frequency components are coupled through
2-2
Theory of Operation-71311 Service
Q82 and C83 to ground, while the desired triggering CR126 is reverse biased and CR129 is forward biased so
component is coupled through Q84 and C87 (as in AC that current flows through Q121 and CR 129 to the trigger
coupling) . tunnel diode and driver circuit.
Trigger Generator Trigger Tunnel Diode and Driver . The trigger tunnel
diode stage shapes the output of the comparator to provide
The trigger generator consists of the Slope Selector and a trigger pulse with a fast leading edge .
Level Comparator, Trigger Tunnel Diode and Driver,
Triggered Lamp multi, TRIG'D Lamp Driver, Trigger
Generator Count Interval Schmitt, Events Schmitt, and Tunnel diode CR141 is quiescently biased so that it is in
Events and Count Coincident Gate . its low-voltage state. Increased trigger current from Q117
and CR 128 or Q121 and CR 129 through R 130, L 130, and
CR141 causes CR141 to switch to the high-voltage state.
Slope Selector and Level Comparator . This stage com- The resulting fast-rise positive step is coupled through
prises Q100, 0102, Q117, Q121 and Q124 . Q100 and emitter-follower Q143 to C182, C145, and C166 in the
Q102 are connected as a differential comparator . The auto multi and trigger generator circuits .
reference voltage for the comparator is selected by the
setting of the LEVEL control, R111 . The internal DC
Balance adjustment, R77, sets the level at the base of 0100 Trig'd Lamp Multi . The Trig'd Lamp Multi stage in-
so that the delaying counter is triggered at the zero-volt cludes Q183 and Q188 . When no trigger is applied, Q183 is
point of the incoming trigger when the LEVEL control is off and C185 is charged to a positive level (at the collector
set to the center of the positive or negative slope region . of Q183) determined by R 184, R 190, and R 191 . The base
The LEVEL control varies the voltage on the base of Q102 of Q192 is more positive than the base of Q194, so Q194 is
to select the point on the trigger signal where triggering conducting .
occurs .
When a trigger is applied, Q183 and Q188 operate as an
R104 establishes the emitter current for Q100 and emitter-coupled monostable multi . Q183 is momentarily
Q102 . Prior to the arrival of a trigger signal, with the turned on by the positive transistion coupled through
LEVEL control set to the center of the positive or negative C 182 .
slope, Q100 and Q102 are passing equal currents .
The collector of Q183 drops and C185 discharges
Assume that a positive-going signal is applied to the EXT through R 185, turning off Q188 . This holds Q183 on for a
TRIG IN connector and that the LEVEUSLOPE control is period determined by the charging time-constant of C185 .
set to zero on the positive slope . If the trigger signal has a repetition rate of 20-hertz or
greater, Q183 stays on (see Fig. 2-2) . With Q183 on, Q192
is also conducting and Q194 is off.
The signal at the EXT TRIG IN connector is inverted by
the trigger preamp, appearing at the base of Q100 as a
negative-going signal . This will cause a decrease in current TRIG'D Lamp Driver . During the time that Q183 is on,
through 0100, and because of the common emitter source, the increased drop across R184 forward biases Q192 . This
R104, the current through Q102 will increase . The de- turns on Q198, which drives the TRIG'D lamp, DS197 .
creased collector current of Q100 biases Q121 in a reverse
direction, while Q117 becomes more forward biased due to
the increased current through Q102 . Trigger Generator. The trigger generator includes Q149,
Q159, CR 169, and CR 171 . The function of this circuit is to
supply a fast-rise trigger signal to the Count Interval
With the SLOPE switch (S2) in the + position, the Schmitt. For normal triggering, this signal is developed after
cathode of CR126 is grounded, forward biasing CR126, receipt of a fast-rise transition from the trigger tunnel diode
which reverse biases CR 129. At the same time, the base of and driver stage, except during holdoff.
Q124 is at ground and 0124 is off. This causes CR122 to
be reverse biased and CR128 is forward biased through
Q117 . An increased current is applied through Q117 and For the following discussion of operation, assume that a
CR128 to the trigger tunnel diode and driver circuit (see trigger signal is applied to the EXT TRIG IN connector.
Fig. 2-1) .
The positive-going transition at the emitter of Q143 is
When the SLOPE switch is set to the - position, Q124 coupled through C182, causing the TRIG'D lamp, DS197
and CR122 are forward biased and CR128 is reverse biased . to be energized as previously described .
REV . B, OCT . 1974 2-3
Theory of Operation-7D11 Service
Fig. 2-1 . Trigger current path for positive slope triggering .
2-4
Theory of Operation-7D11 Service
through a level shifting Schmitt trigger, Q133 and Q138, to
TRIGGER AT an input to U640D . To ensure that events are counted only
BASE OF 0183
when holdoff is not present, the output of CR 171 is also
coupled to an input to U640D through the level shifting
Schmitt trigger formed by Q173 and Q178 . Therefore,
U640D is enabled, during the absence of holdoff, to output
the events count pulses to Q512, the Events Count Source
Gate .
PHASE LOCK LOOP
AND GATED COUNTDOWN
The phase lock loop and gated countdown circuits
Fig . 2-2. Auto Multi input and output waveforms with trigger signal provide the very accurate time count for the 7D11 . In
applied . addition to supplying the timing signal, this circuitry also
provides the fine delay .
CR 169 and CR 171 are both in their high states until the
holdoff signal switches them to the low state . The holdoff
signal is a positive pulse which forward biases both Q149
Phase Lock Loop
and Q159 . When these transistors are forward biased, they
divert current from CR 171 and CR 169, which causes the The phase lock loop is a method of generating a
tunnel diodes to switch to their low states . frequency that is some multiple of an incoming (reference)
frequency . The=n counter divides the local VCO frequency
by some integral number, n . The phase detector compares
The next trigger after holdoff appears as a positive the phase of an incoming signal (see Fig . 2-3) with that of
transition at C145 and C166 . The positive transition, the divided down local voltage controlled oscillator (VCO)
◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo