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>> Download Tektronix_TLA7NA_Series_Datasheet documenatation <<Text preview - extract from the documentTektronix Logic Analyzers
TLA7NAx Logic Analyzer Modules Data Sheet
Applications
Hardware Debug and Verification
Processor/Bus Debug and Verification Including Source Synchronous
Clocking
Embedded Software Integration, Debug and Verification
Breakthrough Solutions for Real-time Digital
Systems Analysis
The TLA7NAx Logic Analyzer Module speeds debug and verification of
fast buses and complex embedded systems with an industry-leading
combination of acquisition, triggering and analysis capabilities. Quickly
debug fast buses like DDR memory and PCI-X, using long record length
to capture intermittent events over a wide time window and MagniVu
high-speed timing to simultaneously capture glitches as small as 125 ps.
The TLA7NAx module's advanced triggering capabilities allow you to
trigger on microprocessor operation failures, which speeds troubleshooting
of embedded systems incorporating microprocessors such as the
PowerQUICCIII. Additional tools like source code and protocol analysis
The TLA Series logic analyzer modules offer the highest performance for today's and listing view make monitoring and debugging processor operation faster
demanding applications. and easier.
Features & Benefits
34/68/102/136 Channel Logic Analyzers with up to 128 Mb Record
Length to Capture Long Periods of Time
500 ps (2 GHz)/32 Mb Timing Analysis to Track Down Elusive Timing
Problems Faster
125 ps (8 GHz) MagniVuTM Acquisition simultaneous with Timing or State
Acquisition to Find Difficult Problems Quickly
Up to 450 MHz State Acquisition Analysis of Synchronous Digital Circuits
Glitch and Setup/Hold Violation Triggering and Display Finds and
Displays Elusive Hardware Problems
Transitional Storage Extends the Signal Analysis Capture Time
Connectorless Probing System With 0.5 pF Capacitive Loading
Eliminates Need For Onboard Connectors, Minimizes Intrusion on
Circuits and is Ideal for Differential Signal Applications
Broad Processor and Bus Support
Data Sheet
Characteristics State Record Length with Time Stamps
Full Channel Half Channel*1
General
512 Kb Standard 1 Mb
Number of Channels (all channels are acquired including clocks)
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