Service Manuals, User Guides, Schematic Diagrams or docs for : Western Digital _dataBooks 1992_SystemLogic_Imaging_Storage 06_WD76C30
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I. ...
WD76C30lLV
TABLE OF CONTENTS
Section Title Page
1.0 DESCRIPTION 6-1
1.1 Features 6-1
1.2 General 6-1
1.3 WD76C30/LV Differences 6-1
1.4 Peripheral Controller 6-2
2.0 PIN DESCRIPTION 6-3
3.0 SERIAL PORT REGISTERS 6-9
3.1 Serial Port Register Addressing 6-9
3.1.1 Chip Select (CSO, CS1) 6-9
3.1.2 Register Select (AO, A 1, A2) 6-9
3.2 ACE Operational Description 6-10
3.2.1 Master Reset 6-10
3.2.2 ACE Accessible Registers 6-50
3.3 Line Control Register 6-13
3.4 ACE Programmable Baud Rate Generator 6-14
3.5 Line Status Register 6-16
3.6 Interrupt Identification Register 6-18
3.7 Interrupt Enable Register 6-10
3.8 Scratch Pad Register 6-20
3.9 FIFO Control Register 6-21
3.10 MODEM Control Register 6-21
3.11 MODEM Status Register 6-23
3.12 FIFO Operation Notes 6-24
3.12.1 FIFO Interrupt Mode Operation 6-24
3.12.2 FIFO Polling Mode Operation 6-24
3.12.3 FIFO Pointer 6-24
4.0 PARALLEL PORT DESCRIPTION 6-25
4.1 Data Register 6-26
4.2 Status Register - Read 6-26
4.3 Control Register - Write 6-27
4.4 Control Register - Read 6-27
5.0 INTERRUPT, CLOCK, AND MODE SELECTION REGISTERS 6-28
5.1 Address Selection Register 6-28
5.2 Clock Selection Register 6-29
5.3 Sleep Mode 6-29
5.4 Clock Disable Register 6-30
5.5 Mode Selection Register 6-31
5.6 Interrupt Multiplexer 6-31
see ADVANCED INFORMATION 11119/91 6-i
WQ76C30lLV
Section Title Page
5.7 SERIAL PORT 0 INTERRUPT SELECTION REGISTER 6-33
5.8 Serial Port 1 Interrupt Selection Register 6-33
5.9 Parallel Port Interrupt Selection Register 6-34
5.10 Version Register 6-34
6.0 ELECTRICAL SPECIFICATIONS 6-35
6.1 Maximum Rating 6-35
6.2 Capacitance 6-35
6.3 DC Operating Characteristics 6-36
6.4 AC Operating Characteristics 6-37
7.0 PACKAGE DIMENSIONS 6-51
I. 8.0 CRYSTAL MANUFACTURES 6-53
8.1 Crystal Specifications 6-53
r.
APPENDIX-A
A.D WD76C30LV DC ELECTRICAL SPECIFICATIONS 6-54
A1 WD76C30LV Maximum Ratings 6-54
A2 Capacitance 6-54
A3 DC Operating Characteristics 6-55
6-ii ADVANCED INFORMATION 11119/91
WD76C30lLV
LIST OF ILLUSTRATIONS
Figure Title Page
1-1 WD76C30 Block Diagram . . . . . 6-2
2-1 84-PIN PLCC Signal/Pin Assignments 6-3
3-1 Interrupt Signal Logic . . . . . . . 6-22
5-1 Interrupt MUX Block Diagram . . . . 6-30
5-2 IROSET When Not In Stand Alone Mode .. 6-32
6-1 Receiver Timing . . . 6-38
6-2 Transmitter Timing . . 6-39
6-3 MODEM Control Timing 6-40
6-4 Read Cycle Timing . . 6-41
6-5 Write Cycle Timing . . 6-41
6-6 RCVR FIFO Signaling Timing for First Byte 6-43
6-7 RCVR FIFO Signaling Timing after First Byte (RBR already set) 6-43
6-8 Parallel Port Timing . . . . 6-44
6-9 Parallel Port Interrupt Timing 6-44
6-10 Clock Generation Timing 6-46
6-11 Interrupt MUX Timing A 6-47
6-12 Interrupt MUX Timing B 6-47
7-1 84-Pin PLCC Package 6-51
7-2 84-Pin POFP Package 6-52
8-1 External Clock Input (8.0 MHz MAX.) 6-53
8-2 Typical Crystal Oscillator Network . 6-53
ADVANCED INFORMATION 11119/91 6-iii
WD76C30lLV
LIST OF TABLES
Table Title Page
2-1 Pin Description ........... . 6-4
3-1 Register Addressing ......... . 6-9
3-2 Reset Control of Registers and Pinout Signals 6-10
3-3 Accessible WD76C30 Serial Port Registers 6-11
3-4 Baud Rates Using 1.8432 MHz Clock 6-14
3-5 Baud Rates Using 3.072 MHz Clock 6-15
3-6 Baud Rates Using 8.0 MHz Clock 6-15
3-7 Interrupt Control Functions . . . . 6-19
4-1 Parallel Port (CS2 = 0) Register Addresses 6-25
4-2 Accessible Parallel Port Registers 6-25
4-3 Parallel Port Operation Modes 6-27
5-1 Clock Selection Register . . . . 6-29
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