Service Manuals, User Guides, Schematic Diagrams or docs for : Western Digital _dataBooks 1992_SystemLogic_Imaging_Storage 03_WD16C550
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SYSTEMS LOGIC/PERIPHERAL
WD16C550
Enhanced Asynchronous
Communications Element (ACE)
with FlFOs
aee WESTERN DIGITAL
WD16C550
TABLE OF CONTENTS
Section Title Page
1.0 INTRODUCTION 3-1
1.1 Description 3-1
1.2 Features 3-1
1.1 General 3-2
2.0 CHIP SELECTION AND REGISTER ADDRESSING 3-4
2.1 Address Strobe (ADS) . . . 3-4
2.2 Chip Select (CSO, CS1, CS2) 3-4
2.3 Register Select (AO, A 1, A2) 3-4
3.0 ACE OPERATIONAL DESCRIPTION 3-5
3.1 Master Reset ..... 3-5
3.2 ACE Accessible Registers 3-5
3.3 Line Control Register 3-8
3.4 ACE Programmable Baud Rate Generator 3-8
3.5 Line Status Register . . . . 3-11
3.6 Interrupt Identification Register 3-12
3.7 Interrupt Enable Register 3-14
3.8 Scratch Pad Register 3-14
3.9 FIFO Control Register . 3-14
4.0 MODEM CONTROL REGISTER 3-15
5.0 MODEM STATUS REGISTER 3-16
6.0 TYPICAL APPLICATIONS . 3-17
7.0 CRYSTAL MANUFACTURERS (Partial List) 3-18
APPENDICES
Section Title Page
A.O Pin Designations 3-20
B.O DC Operating Characteristics 3-25
C.O AC Operating Characteristics and Timing Diagrams 3-27
0.0 Package Diagrams . . . . . . . . . . . . . 3-37
12/1/90 3-i
WD16C550
LIST OF TABLES
Table Title Page
2-1 Register Addressing ..... 3-4
3-1 Reset Control of Registers . . . 3-5
3-2 Accessible WD16C550 Registers 3-6
3-3 Baud Rates Using 1.8432 MHz Clock 3-9
3-4 Baud Rates Using 3.072 MHz Clock 3-9
3-5 Baud Rates Using 8.0 MHz Clock 3-10
3-6 Interrupt Control Functions . 3-13
A-1 Signal Descriptions . . . . 3-21
B-1 DC Operating Characteristics 3-26
B-2 Capacitance ..... . 3-26
C-1 WD16C550 Timing Diagrams 3-27
C-2 Baud Rate Generator Timing 3-28
C-3 Receiver Timing 3-29
C-4 Transmitter Timing 3-30
C-5 Modem Control Timing 3-31
C-6 ReadlWrite Cycle Timing 3-33
3-ii 1211/90
WD16C550
LIST OF ILLUSTRATIONS
Figure Title Page
1-1 40-Pin DIP 3-1
1-2 42-Pin QUAD 3-1
1-3 WD16C550 General System Configuration 3-2
1-4 WD16C550 Block Diagram . . . . . . 3-3
6-1 Typical Interface for a High-Capacity Data Bus 3-17
6-2 Typical i6-Bit Microprocessor/RS-232 Terminal Interface Using the ACE 3-17
7-1 External Clock Input (8.0 MHz Max.) . . . . . . 3-18
7-2 Typical Crystal Oscillator Networks ..... . 3-19
A-1 WD16C550 40-Pin DIP Assembly Pin Designations 3-20
A-2 WD16C550 44-Pin QUAD Assembly Pin Designations 3-20
C-1 Baud Rate Generator Timing 3-28
C-2 Receiver Timing . . 3-29
C-3 Transmitter liming 3-30
C-4 Modem Control liming 3-31
C-5 Read Cycle Timing . 3-32
C-6 Write Cycle Timing . 3-32
C-7 RCVR FIFO Signaling Timing for First Byte 3-34
C-8 RCVR FIFO Signaling Timing after First Byte (RBR Already Set) 3-34
C-9 Receiver DMA Mode 0 Timing 3-35
C-10 Receiver DMA Mode 1 Timing 3-35
C-11 Transmitter DMA Mode 0 liming 3-36
C-12 Transmitter DMA Mode 1 3-36
0-1 40-Pin Lead Plastic "PL" . . . 3-37
0-2 40-Pin Lead Ceramic "AL" . . 3-38
0-3 44-Pin QUAD Lead Plastic "JM" 3-39
12/1/90 3-iii
INTRODUCTION WD16C550
1.0 INTRODUCTION
1.1 DESCRIPTION - Loopback controls for communication
link fault isolation
The WD16C550 is an enhanced programmable
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