Service Manuals, User Guides, Schematic Diagrams or docs for : motorola Mobile Phone E365_sm BD_BlDi_E365_A3_C_L3_1[1].2_030611100711
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GSM 1800 RX
Low Channel - 512 = 1805.2Mhz
(Tx Enable)
Mid Channel - 700 = 1842.8Mhz
High Channel - 885 = 1879.8Mhz T/R Switch GSM_TXEN (VCC)
Control VRF
U103
EGSM RX 6 1 2 U102
Low Channel - 975 = 925.2Mhz CALIBRATION
Mid Channel - 37 = 942.4Mhz AP2 RF PORT 1 (Tx /Rx selection) CH 62 RX Mode
High Channel - 124 = 959.8Mhz 3 3 TRENA RFLO= 947.3Mhz RX IF = 100kHz
4
GSM 1800 TX TX / RX Switch 947,4 MHz 4 22
U201 U203
Low Channel - 512 = 1710.2Mhz CH 62 1 ION 12
Mid Channel - 700 = 1747.8Mhz U101 11 2 2 4
F101 ADC 2 IOP PGA ADC 5 RXIP
High Channel - 885 = 1784.8Mhz Control 6 21 RXIN
11
Channel
Function
Filter
2 IF/100kHz
EGSM TX 4 1
10 GSM_RX 925-960MHz 20
Low Channel - 975 = 880.2Mhz 4 CKP 9 2
Mid Channel - 37 = 897.4Mhz 8 Duplexer 2 RXQP
JP1 1 DCS_RX 1805-1880MHz F102 ADC 3 CKN PGA ADC 3
High Channel - 124 = 914.8Mhz 1 6 19 RXQN
10
2
RF ANTENNA 6, 12 100kHz SPI
o
3 5 0
o
14, 23, 90 1 IF
26, 32 N 6, 20 13 18 17 16 5 14
TX /CH 62
1301.4 MHz 7
PA 13Mhz VRF
GSM 6
TCXOEN
(Clock in) RF_CLK
(Data in) RF_DAT
TXIN
(Data out) SDO_RF
GSMPA 9 7 GSM_TX 25 399MHz
PHASE 399MHz 1
RF_LE
2 R402 1 Exc.
(Enable) PDNB
DET. 5
2 TXIP
CMOS DCS 8
11 1 DCS_TX 24 Exc.
DCSPA
(Enable)
2 R403 1 TXQN
(Latch)
7
TXQP
TX/ CH 62
U401 6 APC (Power Control) 12 13 902,4 MHz 9 10
Control 3 PAENA (Enable)
2 GSM_TXEN (Band Select)
RFLON
RFLOP
4 VBAT (VCC) VSYN
RX /CH 62
1894.6 MHz
5, 25, 28
(Data in) RF_DAT 13
(Clock in) RF_CLK 24 798 MHz
12 SPI RF CH 62
(Latch) RF_LE
(from/to U15)
(Data out) SDO_RF
11 IF VCO 23
10 27 IFLOP
(Enable) PDNB 9 IF
(VCC) VCC4 1 5 VTCXO 7 U301 VCO 26 IFLON
U105 5
U503 4 13Mhz
(Enable) TCXOEN 3 2
(VCC)
VBAT 7 8 VSYN (Tuning/Bias) CH 62 TX Mode
13Mhz_BB
U104 RFLO= 1301,4Mhz
(VCC)
3 AFC IFLO= 798MHz
SXENA 3, 5 6 VRF VTCXO 4 1
(Enable)
U302 TX VCO = 902,4 MHz
Dual Band E365
GSM SERVICE SUPPORT GROUP 2003.05.19 REFERENCE CLOCK
RX SIGNAL PATH
LEVEL 3 RF Block Diagram Rev. 1.2
Revision Overview TX SIGNAL PATH Orderable Part
Rev. 1.0: initial Block Diagram Dual Band - E365
Rev. 1.1: updated SDO_RF signal direction, updated U303 to U503
Rev. 1.2: updated F1 as EMI filter, RF VCO frequency, U201 internal divider, U503 output, TR Switch Michael Hansen Page 1 of 2 MAIN VCO SIGNAL PATH Non - Orderable Part
TUNING VOLTAGES
H11 RF_DAT DISITAL CAMERA CAMERA
VRDBB1.5V
A5,B12,F11,M1,N14,P7
A11,L14,N3,N1,N5
Hercules U15 J14 RF_CLK
Camera IC Connector
J1 VRIO_2.8V POWER Analog / Baseband H14 RF_LE eventuell verbunden auf RF!! U203, U301 RNW B9 DATA BUS DD 0-7 J6
DLPWR A4,B6,D1,G1 SDO_RF
VRMEM_2.8V L12 U18 nFOE B10
PWDN
VACCID SIO3 G13 PDNB F1 4
RX/TX K14 GSM_TXEN D33V 5 nCS4 B10
H4 SCK 10
to/ from Omega SRST3 G10 SIM
3 TDI SCLK3 F13
CNTL K13
M14
TRENA
(to RF Side)
Regulator CLK13M_OUT 2 3 4
CLK13M_DSC E9
U12 D9
SDA
SDO
8
20
14 TCK PAENA
15 TMS TDO, TDI, TMS, TCK JTAG A13 SXENA Regulator E10 SCLK 9
5 TDO A12 TCXOEN U8 DATA BUS D0-7
7 CTS_MODEM C9 CAMERA (to/ from Hercules)
K3 SHS 2
(VCC) VCC4 1 F_1.8 (to Flash)
8 RX_MODEM A9 ADD BUS A1-3
J4 SVS 3
Switch
9 B13 U14 VRRAM_2.8V 2,3 9 VDDS-MIF_2.8V F10 SPCLK 5
TX_MODEM B9 RTC A14 (to U19, Q1, J2) D25V G1, ......
10 UART (enable)
RTS_MODEM E8 ARM 7 ON/ C12 CLK32K_OUT ROW4 6 S22 D33V L2, ...... S25V 6
11 DSR_MODEM D9 OFF B14 COL4 AVDDP B4 DD25V 7
RTC_ALARM
12 DTR_MODEM N3 CNTL AVSSP GND
6 Rx_IrDA D8
F10 SWITCHONOFF Regulator A4 1
D12 RESPWRONZ U13
4 Tx_IrDA C8 D14 VRRTC (VCC) VBAT 1 9 D33V J5
13
VBAT-VCHG 5
U9
1
VBAT M10 COMS_EN 2,3 10 DD25V TFT Display TFTConnector
4 1 C11 nCS4 1,2
1 VCHG IO_PWR_EN L8 S25V NC
(from ext. charger) C1 nCS2 6 LCD_ID 3
KeyLed_En L7 LEDLCM_EN RR26 D25V
EAR_DETECT N11 I/O GPIO L4 L6 AVDDP
GND 4,5
L8 LCD_ID U19 nCS2 6
M4 LCDA0 L7 AVSSP LCDA0 7
(enable) nCS2
(from U303) 13MHZ_BB E13 nBLE U7 RNW 8
E4 (VCC) VDDS-MIF_2.8V 5 3 4 LCD_RD
CLK13M_OUT 2M RAM nBHE
A1
DATA BUS 9
F5 B2 SRAM D0-D12 10-22
(to Display) nRESET RNW DATA BUS
MEM G5 ADD BUS D13-D15 28-26
nRESET TIMER nFOE VDDS-MIF_2.8V 23,24
VRIO_2.8V N2 I/FACE A2 D6, E1, A6 VRRAM_2.8V Boost Power
VBAT CLK13M_OUT F12 nRESET 25
RNW (VCC) VBAT FL1 LED_Anode 29
nIRQ_Melody H10 B2 C5 (Write Enable)
nFOE D6
E2 F8 (Output Enable) LED_Cathode 30
15 7 4 1 3 29 SDO K8 FDP U11
F4 B5 (Reset)
RR1
LS1 3 2
17 U10 30 nSCS0 L9 DAI nCS0 A22 1
BL1 Melody IC 31 SCLK P9 Digtal Audio C2 nCS3 CE U6 (enable) LEDLCM_EN 4
SPKR 4 1
18 U20 E7 FLASH 2 R36
32 SDI M9 Interface D3
AUXO 12,13,14
DSP DATA BUS MEMORY
A5, A4, G4 F_1.8
VCLKRX N12 ADD BUS E1,G6, D6, B4 VRMEM_2.8V
VDX P14 VOICEBAND Key J1/ J2
COL 0 - COL 4
VDR
VFSRX
N13
Interface
Radio
Int. SPI
board
Int.
Keyboard Kepad
M13 ROW 0 - ROW 4
F11 Main Charge Path
Connector
N7, M7, M8
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