Service Manuals, User Guides, Schematic Diagrams or docs for : motorola Mobile Phone E365_sm CD_CiDeCo_E365_A4_C_L3_1[1].0_030610085958
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E365 Theory of Operation
Service Manual
Compal Communications, Inc.
Baseband function Descriptions
1. Introduction
Baby Garnet use TI's chipset (Calypso c035 and IOTA) as base-band
solution. Calypso c035 is a GSM digital base-band logic included
microprocessor , DSP , and peripheral. IOTA is GSM analog/codec solution.
It contains the base-band codec, voice-band codec, several voltage
regulators and SIM level shifter etc. The baby garnet add some features such
as digital camera , photo sensor , TFT display , sixteen tone melody etc.
2. Base-band block
TFT
Color
Display RF- Base_Band Interface ( RIF)
(BBC, APC, AFC,ADAC)
32.768kHz
BACKUP
BATTERY
Ncs2
Tx &Rx I/Q
VBACKUP
TPUPARALLEL
32.768kHz
13M z
H 13M z
H
Miscellaneous
Base band Interface U1 SIM
UART_IRDA
Regulator
UAR O
T_M DERN G /DCS Baseband andV A/Dand
SM oice &Shifter
ARMSERIALPO T
R
U15 D/ARFInterface Circuit W Power
ith
KBR Supply M anagem ent
K AD
EYP Monitoring
Digital baseband processor TPUSERIAL ADC
M TRIX
A KBC (M DC)
A
NCS1
Power Management
PWL JT AP)
AG(T
K AD
EYP
V Band Interface
oice
DAC
BACK H
LIG T
I/O VIBRA R
TO
SIMinterface Interface
LCDBACK H
LIG T
MIC
VCC4
MAIN
NCS0
DATA BUS
ADDRESS
NCS4
BATTERY
NCS3
BUS
Charging function EARN
uWIRE
128Mbits FLASH
nSCS0
NCS1
U6 EARP
AUXI
16Mbits SR N
A
HSO
U7
Melody
ADP TORIN
A VCHG PHONE
IC D IT C M A
IG AL A ER
(DCPower Input) JACK
M elody
Speaker
3. Theory
3.1 CALYPSO
Calypso is a chip implement the digital base-band processes of a GSM/GPRS
mobile phone. The chip combines a DSP sub-chip (LEAD2 CPU) with its
program and data memories, a micro-controller core with emulation
facilities(ARMTDMIE), internal 8Kb of boot ROM memory , 4M bit SRAM
memory , a clock squarer cell, several compiled single-port or 2 ports RAM and
CMOS gates.
3.1.1 Real Time Clock (RTC)
3.1.2 Pulse Width Tones (PWT)
The PWT generates a modulated frequency signal for the external buzzer.
Frequency is programmable between 349Hz and 5276Hz with 12 half tone
frequencies per octave.
3.1.3 Pulse Width Light (PWL)
The PWL allows the control of the backlight of LCD and keypad by
employing a 4096bit random sequence. The block used a switchable clock of
32kHz .
3.1.4 Modem-Uart
3.1.5 I2c master serial interface (I2C)
3.1.6 General purposes I/O (GPIO)
Calypso provides 16 GPIOs in read or write mode by internal registers. In
Baby garnet we use 9 of them as follows.
GPIO PIN Used As.. Description
IO0 / TPU_WAIT IO0 DTR_MODEM Output ; RS232 DTR output signal
IO1 / TPU_IDLE IO1 disable
IO2 / IRQ4 IO2 LEDLCM_EN: LCM backlight=1 active
IO3 / SIM_RnW IO3 LCDA0 ; LCD Data or Command Control signal
IO4 / TSPDI IO4 nIRQ_melody:Melody IC interrupt, active=0
IO5 / SIM_PWCTRL SIM_PWCTRL For SIM Card Power Control
IO6 / BCLKX IO6 EAR_DETECT ; input
IO7 / NRESET_OUT nRESET_OUT ? LCD Peripherals reset
IO8 / MCUEN1 IO8 nIO_PWR_EN: Accessary power control : active=1
IO9 / MCSI_TXD MCSI_TXD DAI interface ,reserved; disable
IO10 / MCSI_RXD IO10 COMS_LDO_EN ; active=1
IO11 / MCSI_CLK IO11 COMS_ASK ; input
IO12/ MCSI_FSYNCH IO12 IO_PWR_EN: Accessary power control : active=1
IO13 / MCUEN2 IO13 LCD_ID; input
IO14 / nBHE nBHE nBHE
IO15 / nBLE nBLE nBLE
3.1.7 Serial Port Interface (SPI)
The SPI is a full-duplex serial port configurable from 1 to 32 bits and
provides 3 enable signals programmable either as positive or negative edge or
level sensitive. We use SPI to control the melody IC.
nSCS0 :Chip select 0
SDO: Data out.
SDI: Data in
SCLK: Serial clock
3.1.8 Memory interface and internal static RAM
A 4Mbit SRAM is embedded on the die and memory mapped on the
chip-select CS6 of the memory interface.
3.1.9 SIM interface
3.1.10 JTAG
3.1.11 Time Serial Port (TSP)
3.1.12 TSP Parallel interface (ACT)
Herculse Pin no Pin Name Used As.. Description/Net
M12 TSPACT0 TP5 X
M14 TSPACT1 TSPACT1 PAENA (Chip enable for
Power Amp IC)
L12 TSPACT2 TSPACT2 PDNB (RF IC power down
control)
L13 TSPACT3 TSPACT3 X
J10 TSPACT4 TSPACT4 X
K11 TSPACT5 TSPACT5 X
K13 TSPACT6/nCS6 TSPACT6 TRENA (T/R switch
enable)
K12 TSPACT7/CLKX_SPI NC X
K14 TSPACT8/Nmreq TSPACT8 GSM_TXEN (Used both
within the RF switch and
the Power Amp to select the
GSM Frequency Band)
J11 TSPACT9/MAS1 TSPACT9 X
J12 TSPACT10/nWAIT NC X
J13 TSPACT11/MCLK NC X
3.1.13 Radio Interface (RIF)
3.2 IOTA
IOTA is an analog base-band device which a digital base-band device is
part of a TI DSP solution intended for digital cellular telephone applications.
This includes the GSM 900, DCS 1800, PCS 1900 standards.
IOTA includes a complete set of base-band functions that perform the
interface and processing of the following voice signals, the base-band in
phase(I) and quadrature (Q) signals. Which support both the single-slot and
multislot modes. IOTA also includes associated auxiliary RF control features
supply voltage regulation, battery charging controls , and switch on/off
system analysis.
IOTA interfaces with the CALYPSO through a digital base-band port and a
voicebad serial port. The signal ports communicate with a DSP core. A
microcontroller serial port communicates with the microcontoller core and a
time serial port communicates with the time processing unit for real-time
control.
3.2.1 Base-band Codec (BBC)
3.2.2 Automatic Frequency Control ( AFC)
3.2.3 Automatic Power Control ( APC)
3.2.4 Time serial port (TSP)
3.2.5 Voice band Codec (VBC)
3.2.6 SIM card shifters (SIMS)
3.2.7 Voltage Regulation (VREG)
Several low-dropout(LDO) linear voltage regulation supply power to
internal analog and digital circuits to the DBB processor and to external
memory
a. VRDBB is a programmable regulator that generates the supply
voltages( 1.8V , 1.5V , and 1.3V) for the core of the CALYPSO. In baby
garnet , it is programmed to 1.5V. During all modes, the main battery directly
supplies VRDBB.
b. VRIO is a programmable regulator that generates the supply voltages(2.8V)
for I/Os of the CALYPSO and IOTA. During all modes, the main battery
directly supplies VRIO.
c. VRMEM is a programmable regulator that generates the supply
voltages(2.8V and 1.8V) for external memories (typically flash memories)
and CALYPSO memory interface I/Os. In baby garnet , it is programmed to
2.8V. During all modes, the main battery directly supplies VRMEM.
d. VRRAM is a programmable regulator that generates the supply
voltages(2.8V and 1.8V) for external memories (typically SRAM memories)
and CALYPSO memory interface I/Os. In baby garnet , it is programmed to
2.8V. During all modes, the main battery directly supplies VRRAM.
e. VRABB is a programmable regulator that generates the supply voltages
(2.8V ) for the analog functions of the IOTA. During all modes, the main
battery directly supplies VRRAM.
f. VRSIM is a programmable regulator that generates the supply voltages
(2.9V and 1.8V )for SIM card and SIM card drivers. During all modes, the
main battery directly supplies VRRAM.
g. VRRTC is programmable regulator that generates the supply voltages
(1.3V, 1.5V ,and 1.8V) for CALYPSO's backup RTC. It is switched on the
main or backup battery, depending on the phone state.
3.2.8 Base-band Serial Port (BSP)
3.2.9 Battery charger interface (BCI)
3.2.10 Monitoring ADC (MADC)
3.2.11 Reference Voltage / Power on control (VRPC)
3.2.12 Internal bus and interrupt controller( IBIC)
3.3power supply circuit
IO TA V R S IM 1 .8 V /2 .9 V S IM card
G S M /D C S B aseb an d V R S A M 2 .8 V
an d Vo ice A /D an d V R M E M 2 .8 V
C A LY P S O
D /A R F In terface V R D B B 1 .5 V
D ig ita l
C ircu it W ith P o w er V R IO 2 .8 V
b a seb an d
S u p p ly M an agem en t V R A B B 2 .8 V
p ro cesso r
V R RT C 1 .5 V
E x tern al 1 .8 v F lash co re 1 2 8 M B it
150m A F lash I/O
E x tern al 2 .8 v
S R A M 1 6 M B it
300m A
LC M
L igh t sen so r
E x tern al 2 .5 v B ack en d co re
150m A I/O
E x tern al 3 .3 v
C m o s sen so r
150m A
The phone is mainly supplied from the main battery. The main battery supply
the two parts : RF block, base-band block.
The input power to IOTA is divided into 4 blocks.
VCRAM: to provide power for VRRAM
VCMEM: to provide power for VRMEM
VCIO1,VCIO2: to provide power for VRIO and VRSIM
VCABB: to provide power for VRABB
VCDBB: to provide power for VRDBB
The IOTA provides seven low drop-out voltage regulators.
VRRAM:2.8V@50mA, to supply SRAM
VRMEM:2.8V@60mA, to supply flash I/O and CALYPSO memory interface
I/Os.
VRDBB;1.5V@120mA. to supply the core of the CALYPSO
VRIO:2.8V@100mA, to supply I/Os of the CALYPSO and IOTA
VRABB;2.8V@50mA to supply the analog functions of the IOTA
VRRTC:1.5V@10uA, to supply the CALYPSO's backup RTC.
VRSIM:1.8V or 2.9V@10mA , to supply the SIM.
3.4 memory circuit
CALYPSO FLASH
Data bus
Address bus
NCS0
NCS3 /CE
NFOE /OE
FDP /RST
RNW /WE
NCS1
NBHE
SRAM
NBLE
/CE
/OE
/HB
/LB
/WE
Description
Flash is a 128Mbit device, supported by external LDO and VRMEM. The
access time of flash is 90ns. The total 128Mbit are divided into two sections:
112Mbit is used for software program code and 16Mbit is used for user's data.
SRAM is a 16Mbit device supported by VRRAM. The access time of flash is
70ns.
3.5 display circuit
VBAT VBAT
VDDS-MIF_2.8V VDDS-MIF_2.8V
DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND
C78 C720 C79 C80 C76 C77 C81 C82 C83 C74 C85
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
C722
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
100PF 0402
D[0..15]
Down
J5
LED_Cathode 30
29 Cathode
1 8 LED_Anode 28 Anode
2 7 R68 27 D13
3 6 200 0408 26 D14
4 5 25 D15
nRESET 24 /RESET
VDDS-MIF_2.8V 23 VCC
1 8 22 VCC
2 7 R69 21 D12
3 6 200 0408 20 D11
4 5 19 D10
1 8 18 D9
2 7 R70 17 D8
3 6 200 0408 16 D7
4 5 15 D6
1 8 14 D5
2 7 R71 13 D4
3 6 200 0408 12 D3
4 5 11 D2
10 D1
9 D0
LCD_RD R75 200 0402 /RD
8
RNW 7 /WR
R76 200 0402
LCDA0 6 RS
nCS2 /CS
R77 100 0402 5
4 GND
3 GND
LCD_ID LCD_ID
2
22PF 0402
22PF 0402
22PF 0402
22PF 0402
NC
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
22PF 0402
1
NC
CON30 Up
C84 C87 C88 C721 C89 C90 C91 C92 C93 C94
DGND
DGND DGND DGND DGND DGND DGND DGND DGND DGND DGND
Description
The display area is a 128*160 resolution LCD module. The power of LCDM
is supplied from external LDO (2.8V). It is controlled by CALYPSO via parallel
interface : data bus and chip select .The Ncs2 is low active to enable the LCDM
data bus. Resistance and capacitance is used for radiation suppression.
3.6vibrater circuit
VBAT
F1 No. G3240010
1
SGM20F1E104-2A 2012
I/O1
4 3
G G
I/O2
2
DGND DGND
3
BQ1
1 2 2 2SC5592 SC59
DAC
R42
1
R43
33 0402
10K 0402
0.95mm
M1
1 MOTOR 4.0*8.8-1.5V-KHN4NZ1D
DGND D4 3930408801W
1SS400 SC79
2
DGND
DAC of the IOTA is used to control the vibrational level. D4 is used to
protection the vibrater. In the 3.8V, the DAC output voltage is 1.9V and drain
current is around 90mA .
3.7 speaker circuit
Description
The Melody IC MA2 works as follows.
First, the CPU (G2) fetch melody data from flash and fed them into MA2
by serial interface. After receiving these data, MA2 will start decode its content
and start its sequencer for processing. After completing this process, the MA2
will generate the tones we want according to the melody data. Then, these data
will run through MA2's DAC, which inside it. Then, the converted signal is fed
into an equalizer, and then followed by an amplifier, which they are inside MA2.
Then this signal will be outputted from SPOUT1 and SPOUT2 to drive the
speaker.
Here, the R44 and R46 provide optimal gain control for MA2. To ensure
the speaker not to be overdrove.
3.8 DSC (Digital Still Camera) function block diagram and circuit
description
3.8.1 Function block diagram
SCCB CF
Backend
(a) Host (d) LCM
(W99688)
(Calypso 035) Toppoly
CMOS
SENSOR
(b) (c) Memory
interface
SRAM
Interface
Data path
Control path
Fig. 1 Imbedded DSC block diagram
Imbedded DSC included two portions, one is front-end sensor module and
another is backend DSP chip. There are including two interfaces which are
SCCB (Serial Camera Control Bus) and CF (Compact Flash). The function
block diagram is shown in Fig.1. The SCCB is used in sensor to backend
interface, and the backend to host (G2) is used CF interface.
3.8.1. Sensor to Backend Interface
CMOS SENSOR
RESET
PWDN
SIO_C
SIO_D
XCLK
Backend
PCLK
VSYNC (W99688)
HSYNC
DATA BUS
RESET: (default 0) chip reset with active high
PWDN: (default 0) power down mode selection
"0" normal mode, "1" power down mode
SIO_C: SCCB (Single Chip Camera Bridge) serial interface clock input
SIO_D: SCCB (Single Chip Camera Bridge) serial interface data input and
output
XCLK: Clock input
PCLK: Pixel clock output
VSYNC: Vertical sync output
HSYNC: Horizontal sync output
Data Bus: 8 bits
3.8.1.2 Backend to Sensor
Interface
A0..A3: Compact Flash: Address-0~3 for command
D15..D0: Data bus connect to Host
RD#: Read data or command
WR#: Write data or command
CS#: Chip select
3.8.2 Circuit description
3.8.2.1 Main circuit
ROW4
DGND
DGND
S22
COL4
DD[0..7]
CAMERA
CC8
TP
33nF 0402 TP27 D33V
T
C726
1
DGND
DGND
D25V
100nF 0402
DD2
DD1
DD0
FPC 0.5mm PITCH
CMOS SENSOR MODULE I/F C725
G10
H10
H11
K11
K10
L11
L10
J10
H8
H9
K9
K8
K7
K5
L8
L9
L7
L6
L5
L4
J5
J9
J6
J8
J7
100nF 0402
DGND
MD1
VD3-8
SD4
VSSI-3
SD3
SD2
SD1
SD0
GPIO3
DVS
OV7645FB/TASC
GND-9
GND-8
DHS
DOCLK
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
DFULL
VDDI-2
DVALID
DGND
RR23
J6 DD3 G9 K1
0 0402 NM(Tasc) SD5 VSSI-2
J11 L3
VDDI-3 GND-7
DGND
1 DD4 G11 L2
GND 2 DD5 K4 SD6 VD3-7 L1
HREF 3 DD6 F9 SD7 GND-6 J1
VSYNC 4 RR22 DD7 F11 SD8 VD3-6 H1
PWDN PWDN SD9 GND-5
5 E11 G1
PCLK 0 0402 (OV) GND-10 VDDI-1
6 F10 H2
AVDD 7 S25V RR24 J4 SPCLK VSSI-1 G2
DVDD 8 DD25V 0 0402 NM(Tasc) K3 SVS U12 VD3-5 F1
SIO_D SDA R79 SHS P31 PWDN
9 E10 688CBM3 F2
XCLK 10 H4 SCLK P30 E1 TP25
SIO_C DD0 SCK 47 0402 SCK SCK USBVDD
11 E9 E2 TP26 1
Y0 DD1 SDA SDA DM T
12 D9 E3 TP29 1
Y1 DD2 R80 R81 SDO SDO DP
13 RR16 D11 D1 T
Y2 DD3 VD3-9 USBVSS 1 TP
14 4.7K 0402 4.7K 0402 10K J3 D2 T
Y3 FWAIT# GND-4
DGND
15 K2 C1 TP
GND 16 DD4 D10 FCD# VD3-4 B1
FRST TP
Y4 17 DD5 A1 B11 FRST GPIO15 C2
Y5 18 DD6 A2 D8 FA0 GPIO14 B2
FIOWR#/FSWE#/FCMD
Y6 FA1 GPIO13
FIORD#/FSRE#/XCMD
19 DD7 A3 A11 D3
FREG#/FSWP#/FCLK
Y7 DD25V FA2 GPIO12
FCE2#/FSCLE/XCLK
20 F3 A1 C96
RESET GND-D GPIO11
FIRQ/FSRB#/FWP
A[1..3] G3 C3 1u 0603
B5 VD3-D GPIO10 B3
FCE1#/FSALE
K6 GND-F RESET A2
FD4/XDAT0
FD5/XDAT1
FD6/XDAT2
FD7/XDAT3
FD0/FDAT0
FD1/FDAT1
FD2/FDAT2
FD3/FDAT3
CMOS_CON DD[0..7] VD3-F GND-3
RR20
SDO RR4
AVDDP
AVSSP
GND-1
GND-2
GPIO0
GPIO1
VD3-1
VD3-2
VD3-3
XOUT
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