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OKIPAGE 10i
LED Page Printer
Troubleshooting Manual
with Component Parts List
ODA/OEL/INT
All specifications are subject to change without notice.
CONTENTS
1. OUTLINE.........................................................................................................1
2. TOOLS ............................................................................................................1
3. CIRCUIT DESCRIPTION ................................................................................2
4. TROUBLESHOOTING ..................................................................................36
5. CIRCUIT DIAGRAM ........................................................................................6
6. COMPONENT PARTS LIST
1. OUTLINE
This manual has been written to provide guidance for troubleshooting of the OKIPAGE 10i Printer
(primarily for its printed circuit boards), based on the assumption that the reader has a thorough
knowledge concerning the printer. Read the maintenance manual for this printer, if necessary.
Notes:
1. The power supply board containing a high voltage power supply is dangerous. From the
viewpoint of the safety standards, the local repairing of a defective board is not allowed. Thus,
the objects to be locally repaired as a result of troubleshooting are switches and fuses.
2. Replacement of CPU (MHM2029) is not recommended. If CPU is found to be defective,
board replacement is suggested.
2. TOOLS
For troubleshooting the printer, the tools listed below may be needed in addition to general
maintenance tools.
Tool Remarks
Extension cord kit P/N: 40581901
Oscilloscope Frequency response 100 MHz or higher
Soldering iron A slender tip type, 15-20 watts
-1-
3. CIRCUIT DESCRIPTION
3.1 Outline
The main control board controls the reception of data transferred through a host I/F and processes
command analysis, bit image development, raster buffer read. It also controls the engine and the
operator panel. Its block diagram is shown in Fig. 3-1 and 3-2.
(1) Reception control
OKIPAGE 10i Printer can be equipped with two I/F ports by adding an RS232C I/F or network
I/F option board in addition to the Centronics I/F on the main control board.
Either of the two I/F ports which receives data first can be used automatically.
The other I/F port outputs a busy state signal.
The parallel I/F port can specify the following item when set by the control panel:
I-PRIME: Enabled/Disabled
The serial I/F port can specify the following item when set by the control panel:
Flow control : DTRHI/DTR LO/XONXOFF/RBSTXON
Baud rate : 300/600/1200/2400/4800/9600/19200 (Baud)
Data bit : 7/8 (bits)
Minimum busy time : 200/1000 (ms)
Parity : NONE/ODD/EVEN
An interface task stores all data received from the host into a receive buffer first.
(2) Command analysis processing
The OKIPAGE 10i printers support PCL6 (Hewlett Packard LJ6P compatible).
An edit task fetches data from the receive buffer, analizes commands, and reconstructs the
data in such a way that print data are aligned from up to down and from right to left; then it
writes the resultant data into a page buffer with such control data as print position coordinate,
font type, etc. added.
(3) Font Processing
When one page editing is finished, a developing task makes an engine start and fetches data
from the page buffer synchronizing with a printing operation; then it developes the fetched
data to a bit map as referring to data from a character generator, and writes the resultant data
into the raster buffer (of band buffer structure).
(4) Raster buffer read.
As controlling the engine operation, an engine task sends data from the raster buffer to the
LED head.
-2-
1MB Memory Board RS232C Interface Board Network Interface Board
or or
(Option) (Option) (Option)
Main Control Board For optional board
Multi-Purpose
Feeder (Option)
Program & Font ROM Resident RAM
6MB Mask ROM 512K x 8 DRAM
DATA High Capacity
(2MB) Second Paper
BUS
(32bit) Feeder (Option)
EEPROM Operation Panel
Centronics M Drum Motor
Drum motor &
parallel I/F
Registration motor
drive circuit
M Registration Motor
7407
1 Chip CPU
FAN Driver FAN
FAN ALM
LED Head
HEAT ON
+8V -8V 0V +5V +30V
Reset
circuit
Power Supply
Cover
Board
open
Inlet sensor 1 switch Charge roller
Transfer roller
Inlet sensor 2 Low voltage
generation circuit
High voltage
generation Developping
circuit roller
Paper sensor
Toner supply
roller
Outlet sensor LSI
Cleaning
roller
Paper out sensor Thermistor
Fusing temperature
control circuit
Toner low sensor Heater drive
Heater
circuit
AC
transformer Filter circuit AC IN
Figure 3-1 Block Diagram
-3-
A2 to A23 ALS244
D0 to D31
ALS244
PD2, 3
OPTION CONNECTOR
PS SIMM or Flash SIMM
DRAM SIMM
BSY
1M Byte
DRAM
SIMM1
SIMM2
CAS0 to
ALS244
CAS3
RAS2 RAS3, 4 RD
RAS2 to ORE WR WR
ALS244
RAS4 WR
ORE, RD,
WR
CS3, EEPCS, EECLK
EEPDAT
IOS1
Figure 3-2 Memory Expansion Board Block Diagram (Option)
-4-
ALS244
A2 to A23
D0 to D31
ALS244
PD2, 3
OPTION CONNECTOR
PS SIMM or Flash SIMM
DRAM SIMM
BSY
SIMM1
SIMM2
CAS0 to
ALS244
CAS3
RAS3, 4 RD
RAS2 to WR WR
ALS244
RAS4
ORE, RD,
WR
CS3, EEPCS, EEPCLK
EEPDAT
IOS1
RXD
RS-232C
75188
TXD, RST, DTR CONNECTOR
Figure 3-3 RS-232C Serial Interface Board Block Diagram (Option)
-5-
ALS244
A2 to A23
D0 to D31
ALS244
PD2, 3
OPTION CONNECTOR
PS SIMM or Flash SIMM
BSY2
DRAM SIMM
BSY1
Flash ROM
LZ9FF22
CS 8900
0.5M Byte
Puls 10 base T
SIMM1
Traus CONNECTOR
CS2
SIMM2
CAS0 to
ALS244
CAS3
RAS3, 4 RD RD
RAS2 to WR WR WR
ALS244
RAS4
ORE, RD,
WR
CS3, EEPCS, EEPCLK
EEPDAT
IOS1
CS2
IOS0
INT2, DMARQ
Figure 3-4 Network Interface Board Block Diagram (Option)
-6-
3.2 CPU and Memory
(1) CPU (MHM2029-004K)
CPU core RISC CPU (MIPS R3000 compatible)
CPU clock 7.067 MHz
Internal CPU CLK 28.268 MHz
(2) Program and Font ROMs
ROM capacity 6M bytes (24M bit mask ROM two pieces)
ROM type 24M bits (1.5M x 16 bits)
Access time 100 ns
(3) Resident RAM
RAM capacity 2M bytes (4-Mbit D-RAM four pieces)
RAM type 4M bits (512k x 8 bits)
Access time 80 ns
(4) Option Board
RAM capacity (chip) 1M byte
RAM type (chip)
Access time (chip)
4M bits D-RAM two pieces
80 ns
} Memory Expansion Board only
SIMM 1 socket 2, 4, 8, 16 or 32M bytes, 72 pin DRAM SIMM, 60 to 100 ns
SIMM 2 socket PS-SIMM or Flash SIMM (72 pin)
Flash ROM capacity (chip) 0.5 M byte
Flash ROM type (chip) 4M bits Flash ROM one pieces
Access time (chip) 100 ns
The block diagram of CPU and memory circuit is shown in Fig. 3-3.
The timing chart of CPU and memory ciucuit is shown in Fig. 3-4.
-7-
CPU
D00 to D32
CS0
CS2
CS3 Option board CS0
CS4
IC2, IC3
Mask ROM
A00 to A25 (1.5M x 16 bits)
2 pieces
RD
RAS0
RAS1
RAS2
RAS3
RAS4
RAS5
RAS0 IC4, IC5, IC6, IC7
CAS0 DRAM
CAS1
(512 k x 8 bits)
CAS2
CAS3 4 pieces
RD/WR
CAS0, 1, 2, 3 Main
control
board
CAS0, 1, 2, 3 RD/WR RAS2, 3, 4, 5 Option
board
DRAM
RAS2 WR 1M Byte
CAS0,1,2,3
(Memory Expansion Board only)
SIMM 1
RAS3, 4 WR DRAM SIMM
CAS0,1,2,3
SIMM 2
PS SIMM or
CS3, RD/WR Flash SIMM
Flash ROM
0.5M byte
CS2, RD/WR
(Network Board only)
Figure 3-8 Block Diagram of CPU & Memory Circuit
-8-
0 17.7 35.4 53.1 70.8 88.4 106.1 123.8 141.5 159.2 176.9 (ns)
(28.268 MHz)
SYSCLK
T1
T2
A00-A25-P VARID VARID
29.32 39.13
T3
T2
DRAS0~5-N
12.25
(DRAS0-N)
27.3 (DRAS1~5-N)
T4
T2
-9-
DCAS0~3-N
T3 14.6
T2
RD-N
17.91
D00~D31-P DATA
Figure 3-9 Timing Chart of CPU & Memory Circuit
TIME
T1 T2 T3 T4 CPU detects the type of SIMM memory installed on the memory
SIMM speed
expansion board, and sets the suitable timing as shown in the left
No SIMM 61.0 ns 162.8 ns 40.7 ns 122.1 ns
handside table.
60 ns 101.7 ns 183.1 ns 61.0 ns 142.4 ns Due to this, T1~T4 values shown above vary depending on the type
of SIMM memory being used.
70 ns 101.7 ns 223.8 ns 61.0 ns 142.4 ns
80 ns 101.7 ns 223.8 ns 61.0 ns 142.4 ns
100 ns 101.7 ns 223.8 ns 61.0 ns 142.4 ns
3.3 Reset Control
When power is turned on, a CLRST-N signal is generated by the rising sequence of +30V and
+8V power supply.
+30V +8V +5V
D2
(15V)
11 172
+ CPU
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