0VP 3.2 CPU and Memory (1) CPU (MSM65917) CPU core nX-8 CPU clock 10 MHz Data bus width External 8 bits, Internal 8 bits (2) Program ROM ROM capacity 64k-bytes (512-kbit EPROM) ROM type 512 kbits (64k x 8 bits) Access time 150 nsec When mask ROM in the CPU is valid, the EPROM is not mounted. (3) Resident RAM RAM capacity 128k bytes (256k x 4 bits D-RAM one piece) or 512k bytes (1M x 4 bits D-RAM one piece) RAM type 1M bits (256k x 4 bits) or 4M bits (1M x 4 bits) Access time 70 ns, 60 ns The block diagram of CPU and memory circuit is shown in Fig. 3-2. -4- CPU IC 6 AD00 to AD07 LS373 A00 to A07 IC3 ALE A08 to A15 IC2 RDN EPROM ROCS (64k x 8 bits) DD00 to DD03 DA00 to DA09 IC11 DA10 DRAM DWR 256k x 4 bits or CAS 1M x 4 bits RAS0 RAS1 RAS2 Main Control Board Figure 3-2 Block Diagram of CPU & Memory in OKIPAGE4w Plus -5- 3.3 Reset Control When power is turned on, RST-N signal is generated by IC5. +5V +5V IC5 CPU 1 63 3 RSTN 2 Power ON Power OFF +5V RST-N -6- 3.4 EEPROM Control The BR93LC46A on the main control board is an electrical erasable/programmable ROM of 64- bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred in units of 16 bits through I/O port (EEPRMDT-P) in serial transmission synchronized with a clock signal from the CPU. IC4 EEPRMDT-P 3 DI DO 39 4 1 EEPROM EEPRMCS-P CPU CS 38 SK EEPRMCLK-P 2 37 The EEPROM operates in the following instruction modes. Instruction Start bit Operation Address Data code Read (READ) 1 10 A5 to A0 Write Enabled (WEN) 1 00 11XXXX Write (WRITE) 1 01 A5 to A0 D15 to D0 Write All Address (WRAL) 1 00 01XXXX D15 to D0 Write Disabled (WDS) 1 00 00XXXX Erase 1 11 A5 to A0 Chip Erasable (ERAL) 1 00 10XXXX Write cycle timing (WRITE) Min. 450 ns CS STATUS SK 1 2 4 9 10 25 DI 1 0 1 A5 A4 A1 A0 D15 D14 D1 D0 Max. 500 ns DO BUSY READY HIGH-Z Max. 10 ms Read cycle timing (READ) CS SK 1 2 4 9 10 25 26 DI 1 1 0 A5 A4 A1 A0 DO 0 D15 D14 D1 D0 D15 D14 HIGH-Z -7- 3.5 Parallel Interface Parallel data is received from a host system via parallel interface which is compliant to the IEEE1284 specification. CN4 65 to 68, 71 to 74 DATA8-P PDATA1-P to PDATA8-P to DATA1-P 64 2 to 9 PSTB-N STB-N IC7 1 78 BUSY-P BUSY-P 11 77 ACK-N ACK-N 10 CPU 79 PE-P PE-P 12 80 SEL-P SEL-P 13 81 FAULT-N FAULT-N 32 82 IPRIME-N IPRIME-N 31 83 SELIN-N SELIN-N 36 84 AUTOFD-N AUTOFEED-N 14 +5V +5V 18 Compatible mode The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data (PDATA1- P to PDATA 8-P) from the parallel port at the fall of PSTB-N signal. Furthermore, it makes the store processing of received data into a receive buffer terminate within a certain fixed time and outputs an ACK-N signal, setting the BUSY-P signal to OFF. PARALLEL DATA (DATA BITs 1 to 8) 0.5