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OKIPAGE8p
LED Page Printer
Troubleshooting Manual
with Component Parts List
       (ODA/OEL/INT)




All specifications are subject to change without notice.
                                                       CONTENTS
1.   OUTLINE..................................................................................................... 1

2.   TOOLS ........................................................................................................ 1

3.   CIRCUIT DESCRIPTION ............................................................................ 2
     3.1     Outline ..................................................................................................................... 2
     3.2     CPU and Memory .................................................................................................... 4
     3.3     Reset Control ........................................................................................................... 6
     3.4     EEPROM Control ..................................................................................................... 7
     3.5     Centronics Parallel Interface .................................................................................... 8
     3.6     Front Operator Panel ............................................................................................... 9
     3.7     LED Head Control ................................................................................................. 10
     3.8     Motor and clutch control ........................................................................................ 12
     3.9     Fuser Temperature Control .................................................................................... 14
     3.10    Sensor Control ....................................................................................................... 17
     3.11    Cover Open ........................................................................................................... 18
     3.12    Power Supply Part ................................................................................................. 19


4.   TROUBLESHOOTING .............................................................................. 21
     4.1     Troubleshooting Table ............................................................................................ 21
     4.2     Troubleshooting Flowchart ..................................................................................... 23


5.   CIRCUIT DIAGRAM .................................................................................. 27

6.   COMPONENT PARTS LIST
1.   OUTLINE

     This manual has been written to provide guidance for troubleshooting of the OKIPAGE8p Printer
     (primarily for its printed circuit boards), on an assumption that the reader is knowledgeable of the
     printer. Read the maintenance manual for this printer if necessary.
     Note:
     1. High voltage power supply board and power supply unit containing a high voltage power
          supply is dangerous. From the viewpoint of the safety standards, the local repairing of a
          defective board is not allowed. Thus, the objects to be locally repaired as a result of
          troubleshooting are switches.

2.   TOOLS

     For troubleshooting the printer, the tools listed below may be needed in addition to general
     maintenance tools.

                      Tool                                     Remarks
       Oscilloscope                   Frequency response 100 MHz or higher
       Soldering iron                 A slender tip type, 15-20 watts




                                                 -1-
3.    CIRCUIT DESCRIPTION

3.1   Outline

      The circuit of OKIPAGE8p consists of a main control board, a main high voltage power supply
      board, a sub-high voltage power supply board and a power supply unit. The block diagram is
      shown in Fig. 3-1. The main control board controls the reception and transmission of data with
      a host I/f and processes command analysis, bit image development, raster buffer read. It also
      controls the engine and high voltage outputs.

      (1) Reception control
          The main control board has one parallel I/F port which is compliant to the IEEE 1284
          specification.
          The parallel I/F port can specify the following item when set by the control panel:
             I-PRIME: Enabled/ Disabled

      (2) Command analysis processing
          The OKIPAGE8p printers support PCL5e (Hewlett Packard LJ6P compatible).
          An edit task fetches data from the receive buffer, analizes commands, and reconstructs the
          data in such a way that print data are aligned from up to down and from right to left; then it
          writes the resultant data into a page buffer with such control data as print position coordinate,
          font type, etc. added.

      (3) Font Processing
          When one page editing is finished, a developing task makes an engine start and fetches data
          from the page buffer synchronizing with a printing operation; then it developes the fetched
          data to a bit map as referring to data from a character generator, and writes the resultant data
          into the raster buffer (of band buffer structure).

      (4) Raster buffer read
          As controlling the engine operation, an engine task sends data from the raster buffer to the
          LED head.

      (5) High voltage control (main, sub)
          The high voltage control circuit in the CPU.

      The high voltage power supply board generates high voltage outputs, and have sensors, LED for
      display.
      The power supply unit generates +26VDC output, +5DC output.




                                                 -2-
                                                                                             Motor
                                                                                              M
                                                    PLUNGER      LED HEAD


                                                       PJ     HEAD1        HEAD2         MOTOR             Main PCB NMA-                            Red
                                                                                                                                                    Amber
                                                                           5V   0V                                                                  Amber
                                                                                       Motor Driver              EEPROM
                                                                                       MTD2005F                    1kb
                                                                                                                                                              0V
      Figure 3-1 OKIPAGE8p Block Diagram




                                                                                                                                                                    OPTION
                                                                                                                                            DRAM 2MB               PCB N4A-
                                                                                         CPU              Serial I/F                                           O
                                                                                                                                              DRAM             P
                                                                                      (NKK3 or 5)                                            1M x 16           T
                                           Parallel                                                                                                            I     DRAM
                                                    CENT
-3-




                                             I/F                                                       Data Bus                                                O    1M x 16
                                                                                                         (x16)                                                 N
                                                               LS07                                   Address Bus        OSC          M-ROM                        DRAM 4MB
                                                                                                                        10MHz         4M x 16
                                                                                                                                    Mask ROM 8MB
                                                                                       OSC
                                                                                       7MHz                         LSI
                                                                                                                 LC26023A       HC244
                                                              +26V +5V 0V 0VP
                                                                                                RST

                                                                      POWER                                            HIVOL              HIVOL2

                                                                                                                                    High Voltage Power Unit
                                                                                                     High Voltage Power Unit                  P6L
                                                                Power Supply Unit                              P2H


                                                                AC                                                              ID Unit
                                                            (120V/ 230V)
                                                                                Heater
                                                                            (Halogen lamp)
3.2   CPU and Memory

      (1) CPU (NKK3 or NKK5)
          CPU core       RISC CPU (MIPS R3000)
          CPU clock       7.067 MHz, Internal CPU CLK 28.268 MHz
          Data bus width External 16 bits, Internal 32 bits

      (2) Program ROM
          ROM capacity       8M-bytes (Mask ROM)
          ROM type           64Mbits (4M x 16 bits)
          Access time        100 nsec

      (3) Resident RAM
          RAM capacity       2M bytes (1Mx 16 bits)
          RAM type           16M bits (1M x 16 bits)
          Access time        60 ns

      (4) Option Board
          RAM capacity       4M bytes (16M bits D-RAM two pieces)
          RAM type           16M bits D-RAM two pieces
          Access time        60 n

      The block diagram of CPU and memory circuit is shown in Fig. 3-2.




                                              -4-
CPU

                                         D00 to D15

      CS0

                                                   CS0


                                                          Mask ROM
                         A00 to A25                      (4M x 16 bits)
                                                          
                                                   RD
  RAS0
  RAS1
  RAS2




                                         RAS0                  DRAM
  CAS0                                                      (1M x 16 bits)
  CAS1

                                          RD/WR

                                        CAS0, 1                              Main
                                                                             control
                                                                             board
            CAS0, 1 WR                RAS1, 2                                Option
                                                                             board


                                                                DRAM
                                      RAS1, 2 WR               4M Byte
                                         CAS0,1




            Figure 3-2 Block Diagram of CPU & Memory in OKIPAGE8p



                                           -5-
3.3     Reset Control

        When power is turned on, RST-N signal is generated by RST.




                            +5V                       +5V



                                      RST                                       CPU

                                  1                                     172
                                            3                                 RSTN


                                  2




                 Power ON                                   Power OFF




          +5V




      CL RST-N




                                                -6-
3.4     EEPROM Control

        The BR93LC46A on the main control board is an electrical erasable/programmable ROM of 64-
        bit x 16-bit configuration. Data input to and output from the ROM are bidirectionally transferred
        in units of 16 bits through I/O port (EEPRMDT-P) in serial transmission synchronized with a clock
        signal from the CPU.


                                                                                                     IC4
                                                                SSTXD-P                     3
                                                                                                DI            DO
                                                      154                                                          4
                                                                                            1  EEPROM
                                                                EEPRMCSO-P
                                            CPU                                               CS
                                                      150
                                                                                                         SK
                                                                EEPRMCLK-P                           2
                                                      151


        The EEPROM operates in the following instruction modes.

                       Instruction                     Start bit                Operation                Address               Data
                                                                                  code

          Read (READ)                                       1                      10                 A5 to A0
          Write Enabled (WEN)                               1                      00                    11XXXX
          Write (WRITE)                                     1                      01                 A5 to A0              D15 to D0
          Write All Address (WRAL)                          1                      00                    01XXXX             D15 to D0
          Write Disabled (WDS)                              1                      00                    00XXXX
          Erase                                             1                      11                 A5 to A0
          Chip Erasable (ERAL)                              1                      00                    10XXXX

        Write cycle timing (WRITE)
                                                                                                           Min. 450 ns
 CS                                                                                                                     STATUS


 SK                1       2                4                         9    10                         25

 DI                1       0       1    A5       A4         A1     A0     D15 D14               D1   D0
                                                                                                                       Max. 500 ns
 DO                                                                                                                    BUSY READY
         HIGH-Z
                                                                                                               Max. 10 ms
        Read cycle timing (READ)


CS

SK             1       2               4                          9       10                         25       26

DI             1       1       0       A5       A4      A1       A0

DO                                                                    0    D15 D14              D1    D0       D15 D14
      HIGH-Z



                                                                      -7-
3.5   Centronics Parallel Interface

      The CPU sets a BUSY-P signal to ON at the same time when it reads the parallel data (PDATA1-
      P to PDATA 8-P) from the parallel port at the fall of PSTB-N signal. Furthermore, it makes the store
      processing of received data into a receive buffer terminate within a certain fixed time and outputs
      an ACK-N signal, setting the BUSY-P signal to OFF.



                                                                                                          CENT
                                  87, 88, 91 to 96
                                                                                                               DATA8-P
                                                     PDATA1-P to PDATA8-P                                        to
                                                                                                               DATA1-P
                                   97                                                            2 to 9
                                                     PSTB-N
                                                                                                               STB-N
                                                                                 Q4                   1
                                   85                PBUSY-P
                                                                                                               BUSY-P
                                                                                                     11
                                   86                PACK-N
                                                                                                               ACK-N
                                                                                                     10
                    CPU            83                PRE-P
                                                                                                               PE-P
                                                                                                     12
                                   81                PSEL-P
                                                                                                               SEL-P
                                                                                                     13
                                   79                PERROR-P
                                                                                                               FAULT-N
                                                                                                     32
                                   80                PINIT-N
                                                                                                               IPRIME-N
                                                                                                     31
                                   82                PSELIN-N
                                                                                                               SELIN-N
                                                                                                     36
                                   84                PALITOFD-N
                                                                                                               AUTOFEED-N
                                                                                                     14


                                                                    +5V or High Level                          +5V
                                                                                                     18




             PARALLEL DATA
             (DATA BITs 1 to 8)
                                                                                       0.5 



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