Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 4553_5553_4625_5625_Quanta_ZQ2_Rev4A
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download Acer Aspire 4553_5553_4625_5625_Quanta_ZQ2_Rev4A documenatation <<
Text preview - extract from the document
1 2 3 4 5 6 7 8
ZQ2 SYSTEM DIAGRAM 01
DDR3-SODIMM1 DDR3 channel A
AMD Champlain CPU THERMAL
PAGE 5,6 SENSOR
35mm X 35mm
A A
S1G4 Processor PAGE 4
DDR3-SODIMM2 DDR3 channel B
638P (PGA)45W/35W
PAGE 5,6 PAGE 2,3,4 CPU_CLK
NBGFX_CLK
NBGPP_CLK CLOCK GEN
SBLINK_CLK
IV@ -----> iGPU
HT3
SW@ -----> dGPU
SP@ -----> option notice
PCI-E
SIDE@ -----> sideport
NORTH BRIDGE
29mm X 29mm
sideport-L75,L76,R583,R392,C832,R455,R550,R502
NB A11-R105,R108 RS880 PAGE 16,17,18
PAGE 22
SB A12-R267,R271 19,20,21
A12 PAGE 7 VGA Park
JV/JM-CN16,R450,R456
B EC-D8,D27 B
(10/100/1000) PAGE 24
UMA-R461
VRAM-R358,R359,R360,R363,R365,R72 PAGE 25 PAGE 26 PAGE 23
PAGE 7,8,9,10
PAGE 23
ALINK X4
PAGE 25
PAGE 27 SOUTH BRIDGE PAGE 32
9
SB820
PAGE 27
AMD CPU CORE (ISL6265)
CPU 4.5W(Ext)
PAGE 36 A11
C 4.3W(Int) C
NB_CORE (UP6111AQDD) PAGE 12,13,14,15,16 0 8 5 4
PAGE 38 NB
PAGE 30 PAGE 23 PAGE 26
+VGPU_CORE (MAX8792ETD)
PAGE 29 10,11,12
PAGE 40
+1V/+1.5_GPU/+1.8_GPU
PAGE 41 PAGE 30
0.9V/DDR 1.5V(RT8207) PAGE 28
PAGE 33
PAGE 39 PAGE 30
SYSTEM 5V/3V (RT8206)
D
PAGE 35 PAGE 30
D
1.1V(UP6111AQDD)
PAGE 37 PAGE 32
PAGE 32 PAGE 32 PAGE 33 PAGE 28 PAGE 28 PAGE 28
Discharge /Thermal protec
Size Document Number Rev
PAGE 42 1A
Block Diagram
Date: Wednesday, May 27, 2009 Sheet 1 of 46
1 2 3 4 5 6 7 8
5 4 3 2 1
+CPUVDDA
02
BLM21PG221SN1D(220,100M,2A)_8 W/S= 15 mil/20mil
S1G4 +2.5V +CPUVDDA CPU_LDT_RST# 300/F_4 R416
L35 CPU CLK CPU_PWRGD 300/F_4 R415 +1.5V
2.5V@250mA CPU_LDT_REQ#_CPU *300/F_4 R412
+1.1V [email protected] +1.1V_VLDT C385 LS0805-100M-N
4.7U/6.3V_6
C387
4.7U/6.3V_6
C379
0.22U/6.3V_4
C380
3300P/50V_4
C386
11 CLK_CPU_BCLKP_PR
CLK_CPU_BCLKP_PR
CLK_CPU_BCLKN_PR CPU_LDT_STOP# 300/F_4 R206
*10U/6.3V_8 11 CLK_CPU_BCLKN_PR
R194 *Short_6
Keep trace from resisor to CPU within 0.6"
R195 *Short_6 +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U24D
U24A W/S= 15 mil/20mil
+CPUVDDA F8 M11
C596 10U/6.3V_8 +1.1V_VLDT +1.1V_VLDT 10U/6.3V_8 C353 CLK_CPU_BCLKP_C R417 169/F_4 CLK_CPU_BCLKN_C +CPUVDDA VDDA1 VSS
D1
VLDT_A0
HT LINK VLDT_B0
AE2 F9
VDDA2 RSVD11
W18
C352 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22U/6.3V_4 C598
D C354 0.22U/6.3V_4 +1.1V_VLDT VLDT_A1 VLDT_B1 +1.1V_VLDT 180P/50V_4 C597 CLK_CPU_BCLKP_PR C608 3900P/25V_4 CLK_CPU_BCLKP_C CPU_SVC_R D
D3 AE4 A9 A6
C599 180P/50V_4 +1.1V_VLDT VLDT_A2 VLDT_B2 +1.1V_VLDT CLK_CPU_BCLKN_PR C609 3900P/25V_4 CLK_CPU_BCLKN_C CLKIN_H SVC CPU_SVD_R
D4 AE5 A8 A4
VLDT_A3 VLDT_B3 CLKIN_L SVD
HT_CADINP0 E3 AD1 HT_CADOUTP0 CPU_LDT_RST# B7
L0_CADIN_H0 L0_CADOUT_H0 11 CPU_LDT_RST# RESET_L
HT_CADINN0 E2 AC1 HT_CADOUTN0 CPU_PWRGD A7
L0_CADIN_L0 L0_CADOUT_L0 11 CPU_PWRGD PWROK
HT_CADINP1 E1 AC2 HT_CADOUTP1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 9,11 CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
SI Change from AMD request HT_CADINN1 F1 AC3 HT_CADOUTN1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_CADINP2 L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUTP2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 AB1 AA8
HT_CADINN2 L0_CADIN_H2 L0_CADOUT_H2 HT_CADOUTN2 MEMHOT_L
G2
L0_CADIN_L2 L0_CADOUT_L2
AA1 SideBand Temp sense I2C 4 CPU_SIC AF4
SIC
HT_CADINP[15..0] HT_CADINP3 G1 AA2 HT_CADOUTP3 AF5
7 HT_CADINP[15..0] L0_CADIN_H3 L0_CADOUT_H3 4 CPU_SID SID
HT_CADINN3 H1 AA3 HT_CADOUTN3 AE6 W7
HT_CADINN[15..0] L0_CADIN_L3 L0_CADOUT_L3 4 CPU_ALERT ALERT_L THERMDC H_THRMDC 4
HT_CADINP4 J1 W2 HT_CADOUTP4 W8
7 HT_CADINN[15..0] L0_CADIN_H4 L0_CADOUT_H4 THERMDA H_THRMDA 4
HT_CADINN4 K1 W3 HT_CADOUTN4 R162 44.2/F_4 CPU_HTREF0 R6
HT_CLKINP[1..0] HT_CADINP5 L0_CADIN_L4 L0_CADOUT_L4 HT_CADOUTP5 R158 44.2/F_4 CPU_HTREF1 HT_REF0
7 HT_CLKINP[1..0]
L3 V1 +1.1V_VLDT P6
HT_CADINN5 L0_CADIN_H5 L0_CADOUT_H5 HT_CADOUTN5 place them to CPU within 1.5" HT_REF1
L2 U1
HT_CLKINN[1..0] HT_CADINP6 L0_CADIN_L5 L0_CADOUT_L5 HT_CADOUTP6 VDDIO_FB_H
7 HT_CLKINN[1..0] L1 U2 36 CPU_VDD0_FB_H F6 W9 VDDIO_FB_H 39
HT_CADINN6 L0_CADIN_H6 L0_CADOUT_H6 HT_CADOUTN6 VDD0_FB_H VDDIO_FB_H VDDIO_FB_L
M1 U3 36 CPU_VDD0_FB_L E6 Y9 VDDIO_FB_L 39
HT_CTLINP[1..0] HT_CADINP7 L0_CADIN_L6 L0_CADOUT_L6 HT_CADOUTP7 VDD0_FB_L VDDIO_FB_L
7 HT_CTLINP[1..0]
N3 T1
HT_CADINN7 L0_CADIN_H7 L0_CADOUT_H7 HT_CADOUTN7
N2 R1 36 CPU_VDD1_FB_H Y6 H6 CPU_VDDNB_FB_H 36
HT_CTLINN[1..0] HT_CADINP8 L0_CADIN_L7 L0_CADOUT_L7 HT_CADOUTP8 VDD1_FB_H VDDNB_FB_H
7 HT_CTLINN[1..0] E5 AD4 36 CPU_VDD1_FB_L AB6 G6 CPU_VDDNB_FB_L 36
HT_CADINN8 L0_CADIN_H8 L0_CADOUT_H8 HT_CADOUTN8 VDD1_FB_L VDDNB_FB_L
F5 AD3
HT_CADOUTP[15..0] HT_CADINP9 L0_CADIN_L8 L0_CADOUT_L8 HT_CADOUTP9 CPU_DBRDY
7 HT_CADOUTP[15..0] F3 AD5 G10
HT_CADINN9 L0_CADIN_H9 L0_CADOUT_H9 HT_CADOUTN9 CPU_TMS DBRDY
F4 AC5 AA9 E10 CPU_DBREQ# R212 *300/F_4 +1.5V
HT_CADOUTN[15..0] HT_CADINP10 L0_CADIN_L9 L0_CADOUT_L9 HT_CADOUTP10 CPU_TCK TMS DBREQ_L R204 300/F_4
7 HT_CADOUTN[15..0]
G5 AB4 AC9 +1.5VSUS
HT_CADINN10 L0_CADIN_H10 L0_CADOUT_H10 HT_CADOUTN10 CPU_TRST# TCK
H5 AB3 AD9 AE9 CPU_TDO
HT_CLKOUTP[1..0] HT_CADINP11 L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUTP11 CPU_TDI TRST_L TDO PV stage:add
7 HT_CLKOUTP[1..0] H3 AB5 AF9
HT_CADINN11 L0_CADIN_H11 L0_CADOUT_H11 HT_CADOUTN11 TDI +1.5VSUS
H4 AA5
HT_CLKOUTN[1..0] HT_CADINP12 L0_CADIN_L11 L0_CADOUT_L11 HT_CADOUTP12 CPUTEST23 option R204
7 HT_CLKOUTN[1..0]
K3 Y5 AD7 J7
HT_CADINN12 L0_CADIN_H12 L0_CADOUT_H12 HT_CADOUTN12 TEST23 TEST28_H for Caspian
K4 W5 H8
HT_CTLOUTP[1..0] HT_CADINP13 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUTP13 CPUTEST18 TEST28_L CPU power
7 HT_CTLOUTP[1..0] L5 V4 H10
C HT_CADINN13 L0_CADIN_H13 L0_CADOUT_H13 HT_CADOUTN13 CPUTEST19 TEST18 CPUTEST17 leakage issue C
M5 V3 G9 D7 T32
HT_CTLOUTN[1..0] HT_CADINP14 L0_CADIN_L13 L0_CADOUT_L13 HT_CADOUTP14 TEST19 TEST17 CPUTEST16
7 HT_CTLOUTN[1..0] M3 V5 E7 T31
HT_CADINN14 L0_CADIN_H14 L0_CADOUT_H14 HT_CADOUTN14 R205 510/F_4 CPUTEST25H TEST16 CPUTEST15
M4 U5 +1.5VSUS E9 F7 T38
HT_CADINP15 L0_CADIN_L14 L0_CADOUT_L14 HT_CADOUTP15 R211 510/F_4 CPUTEST25L TEST25_H TEST15 CPUTEST14
N5 T4 E8 C7 T39
HT_CADINN15 L0_CADIN_H15 L0_CADOUT_H15 HT_CADOUTN15 place them to CPU within 1.5" TEST25_L TEST14
P5 T3
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 C3
HT_CLKINP0 HT_CLKOUTP0 CPUTEST20 TEST21 TEST7
J3 Y1 AF7 K8
HT_CLKINN0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CLKOUTN0 CPUTEST24 TEST20 TEST10
J2 W1 AE7
HT_CLKINP1 L0_CLKIN_L0 L0_CLKOUT_L0 HT_CLKOUTP1 CPUTEST22 TEST24
J5 Y4 AE8 C4
HT_CLKINN1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CLKOUTN1 CPUTEST12 TEST22 TEST8
K5 Y3 AC8
L0_CLKIN_L1 L0_CLKOUT_L1 R384 1K/F_4 CPUTEST27 TEST12
+1.5VSUS AF8
HT_CTLINP0 HT_CTLOUTP0 TEST27 CPUTEST29H
N1 R2 C9 T40
HT_CTLINN0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CTLOUTN0 R383 *300/F_4 R401 *Short_4 TEST9 TEST29_H
P1 R3 C2 C8
HT_CTLINP1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CTLOUTP1 TEST9 TEST29_L
P3 T5 AA6
HT_CTLINN1 L0_CTLIN_H1 L0_CTLOUT_H1 HT_CTLOUTN1 TEST6 R208
P4 R5
L0_CTLIN_L1 L0_CTLOUT_L1
A3 H18 80.6/F_4
FOX PZ63826-284R-41F RSVD1 RSVD10
A5 H19
SOCKET_638_PIN RSVD2 RSVD9 CPUTEST29L
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) B3 AA7 T41
RSVD3 RSVD8
MLX 47296-4131 B5 D5
RSVD4 RSVD7
3..6,36,39,41 +1.5VSUS C1 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2) RSVD5 RSVD6
TYC 4-1903401-2 7,10,26,39,42 +1.5V
7..10,14,37 +1.1V
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) 42 +2.5V
SOCKET_638_PIN
4,5,9..15,19,23,24,26,28..33,35..42 +3V
CNTR_VREF 4 +3V
PV stage:add +1.5VSUS option
C578 0.1U/10V_4
Serial VID R540 R541 for Caspian CPU VFIX MODE VID Override Circuit
+3V R92 20K/F_4 R371 34.8K/F_4 SI Change from AMD request power leakge issue
B R91 B
CNTR_VREF
SVC SVD Voltage Output
4.7K/J_4
0 0 1.1V
2
Q29 *BSS138_NL/SOT23
0 1 1.0V
2
CPU_LDT_REQ#_CPU 1 3 +1.5VSUS R405 1K/F_4
CPU_LDT_REQ# 9
R406 *1K/F_4
CPU_LDT_RST# 1 3 CPU_LDT_RST_HTPA#
+1.5V 1 0 0.9V
Q5 D05
R368 *0_4 BSS138_NL/SOT23 +1.5VSUS R409 *1K/F_4 1 1 0.8V
1
G2 +1.5V R413 1K/F_4
The RS880 family does not support CLMC architecture *SHORT_ PAD1
The LDTREQ# connection from the CPU to ALLOW_LDTSTOP CPU_SVC_R R411 *Short_4
CPU_SVC 36
CPU_SVD_R R408 *Short_4
of the Northbridge is no longer required.
2
CPU_SVD 36
CPU_PWRGD R414 *Short_4
CPU_PWRGD_SVID_REG 36
for debug only
R410 *220/J_4
R407 *220/J_4
+1.5VSUS R95 *10K/F_4 S1g4 does not support MEMHOT# R418 *220/J_4
2
+1.5VSUS R90 *1K/F_4 Q4
*MMBT3904 CPUTEST24 R381 1K/F_4
CPU_MEMHOT_L# 3
R152
1
*0_4
CPU_MEMHOT# 5,11 HDT Connector CPUTEST23
CPUTES◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo