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A B C D E
1 1
Compal Confidential
2 2
NAL90/NALG0 M/B Schematics Document
Intel Auburndale/Clarksfield Processor with DDRIII + Ibex Peak-M
3 2009-10-20 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 1 of 60
A B C D E
A B C D E
Clock Generator
Compal Confidential IDT: 9LRS3199AKLFT
Model Name NALG0 SILEGO: SLG8SP587
133/120/100/96/14.318MHZ to PCH
File Name : LA5681P Fan Control
page 41
48MHZ to CardReader
page 12
1 1
100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel Memory BUS(DDRIII)
Nvidia N11MGE1 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
HDMI(DIS) Auburndale / Clarksfield BANK 0, 1, 2, 3 page 10,11
page LVDS(DIS) 1.5V DDRIII 800/1066/1333
22,23,24,25,26,27 CRT(DIS) (UMA/DIS) (DIS) 6.4G/8.5G/10.6G
100M/133M/166M(CFD)
Processor
rPGA988A
page 4,5,6,7,8,9
USB conn x2 Bluetooth CMOS Finger Card
FDI x8 DMI x4 USB port 8 HS Printer Reader
(UMA) USB Port 2 (eSATA)
Conn Camera
HDMI Conn. CRT Conn. CRT LVDS Conn. LVDS USB port 10 USB port 3 USB port 11 USB port 6
100MHz 100MHz USB port 0 (sub board)
page 30
page 29
SW
page 29 page 28
SW
page 28 2.7GT/s 1GB/s x4
page 35 page 35 page 28 page 35 page 36
2 USBx14 3.3V 48MHz 2
LVDS(UMA)
Intel 3.3V 24MHz
CRT(UMA) HD Audio
Level Shift Ibex Peak-M
HDMI(UMA) SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz
page 30
PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S) 100MHz PCH HDA Codec MDC
page 13,14,15,16,17
18,19,20,21 ALC888 page 39
port 2,4 port 1 SPI page 40
MINI Card x2 LAN(GbE) port 0 port 1 port 4
WLAN, TV BCM57780 SATA HDD SATA ODD eSATA
SPI ROM x2 Audio AMP
page 32 page 33
page 13
Conn. Conn. Conn.
page 31 page 31 page 35
APA2051
page 41
3
RJ45 LPC BUS 3
page 34
33MHz
Int. Speaker
ENE KB926 page 41
page 37
NAL90 Sub-board NALG0 Sub-board
RTC CKT. LS-5682P LS-5682P
page 8 USB/B USB/B
page 35 page 35 Touch Pad Int.KBD
page 38 page 38
Power On/Off CKT. LS-4493P
Media/B
page 8 page 38 BIOS ROM
page 38
LS-5683P LS-5683P
DC/DC Interface CKT. Function/B Function/B
page 38 page 38
4 4
page 42
LS-5681P LS-5681P
Finger Printer/B Finger Printer/B
Power Circuit DC/DC page 35 page 35
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
page Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 2 of 60
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON ON OFF
+GFX_core Core voltage for CPU ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.1VS_VTT 1.1V switched power rail (1.05 for AUB CPU) ON OFF OFF
+VGA_CORE Core voltage for N11M VGA ON OFF OFF
+1.05VS 1.05V switched power rail for PCH ON OFF OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V power rail for DDRIII ON ON OFF Vcc 3.3V +/- 5%
+0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5VS 1.5V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.8VS 1.8V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
7 NC 2.500 V 3.300 V 3.300 V
2 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
BOARD ID Table BTO Option Table
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BTO Item BOM Structure
Board ID PCB Revision
0
UMA UMA@
0.1
UMA only UMA only@
External PCI Devices 1 0.2
DIS DIS@
2 0.3
Device IDSEL# REQ#/GNT# Interrupts DIS Only DIS only@
3 1.0 Switchable SG@
4
5
XDP@
6
NonSG@
7
MINI2@
FP@
USB Port Table eDriver@
EC SM Bus1 address EC SM Bus2 address Dmic@
4 External
3 USB 2.0 USB 1.1 Port USB Port 3
Device Address Device Address
Smart Battery 0001 011X b PCH
Caps@
0 Ext4 HS USB
VGA
UHCI0 X76@
1 sub Board
HDCP@
2 AMIC@
UHCI1
S3 power S3@
3 Camera
EHCI1 non S3@
4 1st Min-Card
UHCI2
Ibex SM Bus address 5 2st Min-Card
6 BOM Config
Device Address UHCI3 UMA only
7 UMA@/UMA only@/FP@/Dmic@/XDP@/S3@
Clock Generator 1101 0010b
(9LRS3199AKLFT, SLG8SP587) 8 Ext4 HS USB
DDR DIMM0 1001 000Xb
UHCI4
9 Card Reader
DDR DIMM2 1001 010Xb
DIS ONLY
10 Blue Tooth DIS@/DIS only@/FP@/Dmic@/XDP@/S3@
Mini card
EHCI2 UHCI5
11 Finger Print
12
4 UHCI6 Switchable Graphics 4
13 SG@/UMA@/DIS@/FP@/Dmic@/XDP@/S3@
Note:do cost BOM add X76@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2009/5/12 Deciphered Date 2010/04/15 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
NALG0 M/B LA-5681P Schematic
Date: Friday, October 23, 2009 Sheet 3 of 60
A B C D E
5 4 3 2 1
JCPU1E
JCPU1A R520 AJ13
PEG_IRCOMP RSVD32
PEG_ICOMPI B26 1 2 49.9_0402_1% RSVD33 AJ12
PEG_ICOMPO A26
DMI_PTX_HRX_N0 A24 B27 R535 AP25
DMI_PTX_HRX_N1 DMI_RX#[0] PEG_RCOMPO EXP_RBIAS RSVD1
C23 DMI_RX#[1] PEG_RBIAS A25 1 2 750_0402_1% AL25 RSVD2 RSVD34 AH25
DMI_PTX_HRX_N2 B22 AL24 AK26
DMI_PTX_HRX_N3 DMI_RX#[2] PEG_GTX_C_HRX_N15 RSVD3 RSVD35
A21 DMI_RX#[3] PEG_RX#[0] K35 AL22 RSVD4
J34 PEG_GTX_C_HRX_N14 AJ33 AL26
DMI_PTX_HRX_P0 PEG_RX#[1] PEG_GTX_C_HRX_N13 RSVD5 RSVD36
B24 DMI_RX[0] PEG_RX#[2] J33 AG9 RSVD6 RSVD_NCTF_37 AR2
DMI_PTX_HRX_P1 D23 G35 PEG_GTX_C_HRX_N12 M27
DMI_RX[1] PEG_RX#[3] RSVD7
DMI
DMI_PTX_HRX_P2 B23 G32 PEG_GTX_C_HRX_N11 L28 AJ26
DMI_PTX_HRX_P3 DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10 RSVD8 RSVD38
D A22 DMI_RX[3] PEG_RX#[5] F34 10 H_DIMMA_REF J17 SA_DIMM_VREF (CFD Only) RSVD39 AJ27 D
F31 PEG_GTX_C_HRX_N9 H17
PEG_RX#[6] 11 H_DIMMB_REF SB_DIMM_VREF (CFD Only)
DMI_HTX_PRX_N0 D24 D35 PEG_GTX_C_HRX_N8 G25
DMI_HTX_PRX_N1 DMI_TX#[0] PEG_RX#[7] PEG_GTX_C_HRX_N7 RSVD11
G24 DMI_TX#[1] PEG_RX#[8] E33 G17 RSVD12
DMI_HTX_PRX_N2 F23 C33 PEG_GTX_C_HRX_N6 E31 AP1
DMI_HTX_PRX_N3 DMI_TX#[2] PEG_RX#[9] PEG_GTX_C_HRX_N5 RSVD13 RSVD_NCTF_40
H23 DMI_TX#[3] PEG_RX#[10] D32 E30 RSVD14 RSVD_NCTF_41 AT2
B32 PEG_GTX_C_HRX_N4
DMI_HTX_PRX_P0 PEG_RX#[11] PEG_GTX_C_HRX_N3
D25 DMI_TX[0] PEG_RX#[12] C31 RSVD_NCTF_42 AT3
DMI_HTX_PRX_P1 F24 B28 PEG_GTX_C_HRX_N2 AR1
DMI_HTX_PRX_P2 DMI_TX[1] PEG_RX#[13] PEG_GTX_C_HRX_N1 RSVD_NCTF_43
E23 DMI_TX[2] PEG_RX#[14] B30
DMI_HTX_PRX_P3 G23 A31 PEG_GTX_C_HRX_N0
DMI_TX[3] PEG_RX#[15]
J35 PEG_GTX_C_HRX_P15 R74 AL28
PEG_RX[0] PEG_GTX_C_HRX_P14 3.01K_0402_1% RSVD45
PEG_RX[1] H34 1 @ 2 CFG0 AM30 CFG[0] RSVD46 AL29
H33 PEG_GTX_C_HRX_P13 AM28 AP30
H_FDI_TXN0 PEG_RX[2] PEG_GTX_C_HRX_P12 R72 CFG[1] RSVD47
E22 FDI_TX#[0] PEG_RX[3] F35 AP31 CFG[2] RSVD48 AP32
H_FDI_TXN1 D21 G33 PEG_GTX_C_HRX_P11 3.01K_0402_1% 1 DIS@ 2 CFG3 AL32 AL27
H_FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_GTX_C_HRX_P10 R75 CFG[3] RSVD49
D19 FDI_TX#[2] PEG_RX[5] E34 1 @ 2 CFG4 AL30 CFG[4] RSVD50 AT31
H_FDI_TXN3 D18 F32 PEG_GTX_C_HRX_P9 3.01K_0402_1% AM31 AT32
H_FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_GTX_C_HRX_P8 CFG[5] RSVD51
G21 FDI_TX#[4] PEG_RX[7] D34 AN29 CFG[6] RSVD52 AP33
H_FDI_TXN5 PEG_GTX_C_HRX_P7 R71 1 @ CFG7
H_FDI_TXN6
E19
F21
FDI_TX#[5]
FDI_TX#[6]
PCI EXPRESS -- GRAPHICS PEG_RX[8]
PEG_RX[9]
F33
B33 PEG_GTX_C_HRX_P6 3.01K_0402_1%
2 AM32
AK32
CFG[7]
CFG[8]
RSVD53
RSVD_NCTF_54
AR33
AT33
Intel(R) FDI
H_FDI_TXN7 G18 D31 PEG_GTX_C_HRX_P5 AK31 AT34
RESERVED
FDI_TX#[7] PEG_RX[10] PEG_GTX_C_HRX_P4 CFG[9] RSVD_NCTF_55
PEG_RX[11] A32 AK28 CFG[10] RSVD_NCTF_56 AP35
C30 PEG_GTX_C_HRX_P3 WW41 Recommend not pull down AJ28 AR35
H_FDI_TXP0 PEG_RX[12] PEG_GTX_C_HRX_P2 CFG[11] RSVD_NCTF_57
D22 FDI_TX[0] PEG_RX[13] A28 PCIE2.0 Jitter is over on ES1 AN30 CFG[12] RSVD58 AR32
H_FDI_TXP1 C21 B29 PEG_GTX_C_HRX_P1 AN32
H_FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_GTX_C_HRX_P0 CFG[13]
D20 FDI_TX[2] PEG_RX[15] A30 AJ32 CFG[14]
H_FDI_TXP3 C18 AJ29 E15
C H_FDI_TXP4 FDI_TX[3] PEG_HTX_GRX_N15 C473 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N15 CFG[15] RSVD_TP_59 C
G22 FDI_TX[4] PEG_TX#[0] L33 1 2 AJ30 CFG[16] RSVD_TP_60 F15
H_FDI_TXP5 E20 M35 PEG_HTX_GRX_N14 C475 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N14 AK30 A2
H_FDI_TXP6 FDI_TX[5] PEG_TX#[1] PEG_HTX_GRX_N13 C470 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N13 CFG[17] KEY R214
F20 FDI_TX[6] PEG_TX#[2] M33 1 2 H16 RSVD_TP_86 RSVD62 D15
H_FDI_TXP7 G19 M30 PEG_HTX_GRX_N12 C458 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N12 C15 0_0402_5%
FDI_TX[7] PEG_TX#[3] PEG_HTX_GRX_N11 C454 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N11 RSVD63 RSVD64_R 2 @
PEG_TX#[4] L31 1 2 RSVD64 AJ15 1
F17 K32 PEG_HTX_GRX_N10 C447 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N10 AH15 RSVD65_R 2 @ 1
15 H_FDI_FSYNC0 FDI_FSYNC[0] PEG_TX#[5] RSVD65
E17 M29 PEG_HTX_GRX_N9 C460 1 2 DIS@ 0.1U_0402_16V7K PEG_HTX_C_GRX_N9 R213
15 H_FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
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