Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 4741ZG_eMachines_D730_Wistron_HM42-CP_RevSC
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5 4 3 2 1
Project code: 91.4GW01.001(HM42-CP)
+0&3 %ORFN PCB P/N : 48.4GW01.011 X3
27Mhz
91.4GY01.001(JE40-CP)
91.4GZ01.001(SJV41-CP)
SYSTEM DC/DC
RT8223
REVISION : -1 09920 91.4JD01.001(BA40-CP) INPUTS OUTPUTS
'LDJUDP DCBATOUT
5V_S5
3D3V_S5
Clock Generator Intel CPU 24 49
RGB CRT
CRT
ICS9LRS3197AKLFT DDRIII Slot 0 DDRII Channel A
D
N11P-GE1 SYSTEM DC/DC D
3 800/1066 20
Arrandale N11M-GE1 RT8209E
PCI EXPRESS GRAPHIC LVDS 1CH
LCD
INPUTS OUTPUTS
DDRIII Slot 1 DDR II Channel B 4,5,..,9,10 WXGA+ 23
X16
800/1066 21
Nvida 25 DCBATOUT 1D5V_S3
X2 HDMI
HDMI 50
14.318Mhz 22
FDIx8 DMIx4 SYSTEM DC/DC
RT8209E
INPUTS OUTPUTS
WEBCAM JE40_Power_ BD
23
1D05V_VTT
Mini-Card INTEL 09738-1 DCBATOUT 1D05V_S0
PCIE 51
WLAN 38
BLUETOOTH
29
PCH HM42_Power_ BD SYSTEM DC/DC
RT9025
14 USB 2.0/1.1 ports USB 2.0
09737-1
Mini-Card USB x 3 30
INPUTS OUTPUTS
USB 2.0
C 3G ETHERNET (10/100/1000Mb) C
38
High Definition Audio SJV41_Power_ BD DCBATOUT 1D8V_S0
52
6 SATA ports
USB_BD
09740-1
8 PCIE ports
09736-1 SYSTEM DC/DC
Giga LAN
RJ45 PCIE ACPI 1.1
RT8209E
CONN 32 BCM57780 SJV41_LED_ BD INPUTS OUTPUTS
LPC I/F
31 09739-1
PCI/PCI BRIDGE DCBATOUT VGA_CORE
55
X1
X5
25Mhz Card Reader
25Mhz SD/MMC 37 SYSTEM DC/DC
AU 6433
37
MS/MS Pro/xD TPS5161
INPUTS OUTPUTS
MIC IN HD AUDIO
CODEC AZALIA SATA SATA HDD 26 DCBATOUT VCC_GFXCORE
47,48
INT MIC ALC272 33
B B
CPU DC/DC
PCB STACKUP ISL62882C
SPI INPUTS OUTPUTS
TOP SATA ODD 27
OP AMP 11,12,...,18,19 DCBATOUT VCC_CORE
GND 47,48
G1454 34
S X6
32.768Khz LPC Bus LPC debug 41
S Flash ROM CHARGER
GND LINE OUT 4MB 41 ISL88731C
BOTTOM KBC INPUTS OUTPUTS
X4 BA40_Power_ BD
ENE 3930 32.768Khz
SPI 09768-1
40 DCBATOUT BT+
2CH SPEAKER 53
A Diserete N11M A
Thermal Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Flash ROM Touch Int.
Sensor 39 Taipei Hsien 221, Taiwan, R.O.C.
128KB 41 PAD43
KB40 Title
G792
Block Diagram
CPU FAN Size Document Number Rev
A3
HM42-CP SC
Date: Friday, January 22, 2010 Sheet 1 of 72
5 4 3 2 1
A B C D E
PCH Strapping Processor Strapping
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k Embedded DisplayPort.
- 10-k weak pull-up resistor. DisplayPort
Presence 0: Enabled - An external Display Port device is
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
4 GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
4
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1# required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-k pull-down
resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k samples. MoW and sighting report].
pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-k
pull-down resistor.
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
3 Disable iTPM: Left floating, no pull-down required. 3
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden.
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter
circuits for analog rails.
2 2
USB Table
PCIE Routing
Pair Device
LANE1 LAN 0 USB3
LANE2 MiniCard1 1 USB2
2 USB4
LANE3 MiniCard2 3 MINICARD1
4 WECAM
5 Touch Panel
6 NC
7 NC
8 NC
9 USB1(HS)
10 Finger Print
1 11 Blue Tooth 1
12 MINIC2 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
13 Cardreader Taipei Hsien 221, Taiwan, R.O.C.
Title
Table of Content
Size Document Number Rev
A3
HM42-CP SC
Date: Friday, January 22, 2010 Sheet 2 of 72
A B C D E
1D5V_S0_CLKGEN
0113 -1
1D5V_S0_CLKGEN
C366
1130 -SC
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C361 C359
SC10U6D3V3MX-GP
1D5V_S0 R3111 2
0R3J-0-U-GP 1D05V_S0
2
2
2
0R0603-PAD
0120 -1 1 2
R307
3D3V_S0 3D3V_S0
4 0R0603-PAD 1130 -SC 4
1 2 3D3V_CK505 1 DY 2 3D3V_CK505_IO R3061 2
R310 C360 C355 0R3J-0-U-GP
1
1
1
1
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C356 R308 C357 C358 C354
DY
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
0R3J-0-U-GP DY C353 DY
SC1U10V2ZY-GP
2
2
2
2
2
2
2
1130 -SC SA 0622 EMI
VGA_XIN1_L 1 2
OSC_SPREAD_L DY EC49
1 2 SC22P50V2JN-4GP
DY EC48 SC22P50V2JN-4GP
U16 1130 -SC
1D5V_S0_CLKGEN 1 10 CLK_PCIE_SATA_R 2 0R0402-PAD R371
1 CLK_PCIE_SATA 12
3D3V_CK505 VDD96_1_5 SATAT_LR CLK_PCIE_SATA#_R2 0R0402-PAD R695
5 VDD27_3_3 SATAC_LR 11 1 CLK_PCIE_SATA# 12
3D3V_CK505_IO 15 VDDPCIEX_IO_LV
17 VDDPCIEX_1_5
18 3 DREFCLK_R 2 0R0402-PAD R547
1 DREFCLK 12
VDDCPU_IO_LV DOT96T_LR DREFCLK#_R 0R0402-PADR411
1118 -SC 24 VDDCPU_1_5 DOT96C_LR 4 2 1 DREFCLK# 12
29 VDDREF_3_3
RNT1 23 CLK_CPU_BCLK_R 2 0R0402-PAD R697
1 CLK_CPU_BCLK 12
3 VGA_XIN1_L CPUT_LR0 CLK_CPU_BCLK#_R0R0402-PAD1 R696 3
62 VGA_XIN1 1 4 6 27FIX CPUC_LR0 22 2 CLK_CPU_BCLK# 12
62 OSC_SPREAD SRN33J-5-GP-U 2 DY 3 OSC_SPREAD_L 7 20
27SS CPUT_LR1
CPUC_LR1 19
12,20,21 PCH_SMBCLK 32 SCLK_3_3
12,20,21 PCH_SMBDATA 31 13 CLKIN_DMI_R 2 0R0402-PAD R367
1 CLKIN_DMI 12
SDATA_3_3 PCIEXT_LR CLKIN_DMI#_R
PCIEXC_LR 14 2 0R0402-PAD R548
1 CLKIN_DMI# 12
GEN_XTAL_IN 28
GEN_XTAL_OUT X1
27 X2 GND96 2
GND27 8
GNDSATA 9
R316 CLK_EN 25 12 SA 0629 RF
FSC VTTPWRGD/PD#_3_3 GNDPCIEX
12 CLK_ICH14 2 1 30 REF/FSLC GNDCPU 21 1130 -SC
GNDREF 26 DY
C365 33R2J-2-GP CPU_STOP# 16 33 PCH_SMBDATA 1 2
NC#16 GND
1
3D3V_S0 ECT3 SC33P50V2JN-3GP
DY
SC4D7P50V2CN-1GP
DY
9LVS3197BKLFT-GP PCH_SMBCLK 1 2
2
71.93197.B03 ECT4 SC33P50V2JN-3GP
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