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A B C D E
Compal Confidential
Model Name : JM40-HR
File Name : LA-7231P
1 1
2 Compal Confidential 2
JM40-HR M/B Schematics Document
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
Nvidia N12P-GS/GV-OP
3 3
2010-02-22
REV:1.0
ZZZ
Part Number Description
DAZ0IO00100
P4LJ0_PCB
PCB P4LJ0 LA-7231P LS-7231P/7233P/7235P/7237P
ZZZ
Part Number Description
DC30100DT00 DC_IN_CABLE_90W
4 P4LJ0_DCIN_CABLE_90W 4
90W@
ZZZ
Part Number Description
DC30100DS00 DC_IN_CABLE_65W Security Classification Compal Secret Data Compal Electronics, Inc.
P4LJ0_DCIN_CABLE_65W 2010/09/28 2011/09/28 Title
65W@
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 1 of 57
A B C D E
A B C D E
P4LJ0 Block Diagram Fan Control
page 38
1 1
100MHz PCI-E 2.0x16 5GT/s PER LANE
PEG(DIS) Intel Memory BUS(DDRIII)
VRAM * 8 133MHz Dual Channel 204pin DDRIII-SO-DIMM X2
Nvidia N12P-GS/GV Sandy Bridge BANK 0, 1, 2, 3 page 11,12
DDR3 973pin BGA 1.5V DDRIII 1066/1333
Processor
64*16
128*16 page22~30 DC/QC 35W
EDP SV
(reserved)
page 32
rPGA989
page 4~10
HDMI(Reserved Only) USB 2.0 conn x2 Bluetooth CMOS Camera Mini Card
FDI x8 DMI x4
Conn (WWAN,SIM)
USB port 0,1 on USB/B USB port 13 USB port 10 USB port 9,12 on 3G/B
HDMI Conn. CRT Conn. LVDS Conn. 100MHz 100MHz
page 37 page 37 page 31 page 37
page 33 page 32 page 31 2.7GT/s 1GB/s x4
3.3V 48MHz
2 USBx14 2
HDMI(UMA/Optimus) LVDS(UMA/Optimus)
Intel
CRT(UMA/Optimus) HD Audio 3.3V 24MHz
TMDS(UMA/Optimus) Cougar Point-M
100MHz
PCH
PCI-Express x 8 (ARD PCIE2.0 2.5GT/s)
HDA Codec
port 4 port 3 port 2 port 1 SATA x 6 100MHz 989pin BGA CX20584
page 43
(GEN1 1.5GT/S ,GEN2 3GT/S) page 13~21 SPI
USB 3.0 controller MINI Card x1 LAN(GbE)
UPD720200AF1 WLAN
USB port 8 AR8151
+ Charger page 46 page 37 page 35
SPI ROM x1
port 2 page 14
Card Reader port 0
SATA HDD SATA CDROM
RTS5209 RJ45
USB 3.0 Conn. Conn. Int. Speaker DMIC MIC Jack HP/SPDIF
3 page 38 page 36 page 34 page 34 LPC BUS 3
conn x1 33MHz
on USB/B Jack on USB/B
page 46 page 43 page 43 page 37 page 37
Sub-board ENE KB930
page 39
LS-7231P LS-7237P
RTC CKT. Power/B Door/B
page 41 page 40
page 13
Touch Pad Int.KBD
page 40 page 40
Power On/Off CKT. LS-7235P/7236P
page 40 USB_Auido/B
USB Port0,1 page 37
BIOS ROM
page 39
DC/DC Interface CKT. LS-7233P
4
page 45 FUN/B 4
page 41
Power Circuit DC/DC LS-7234P
page 47~55 3G Security Classification Compal Secret Data Compal Electronics, Inc.
USB Port9,12 page 37 Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 2 of 57
A B C D E
A B C D E
SIGNAL
Voltage Rails STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Power Plane Description S1 S3 S5 Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VIN Adapter power supply (19V) N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+VGFX_CORE Core voltage for UMA graphic ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF
+1.05VSDGPU +1.05VSDGPU power rail for GPU ON OFF OFF
+1.05VS_VCCP +1.05VS_VCCPP to +1.05VS_VCCP switched power rail for CPU ON OFF OFF Board ID/ Project ID Table for AD channel
+1.05VS_PCH +1.05VS_VCCP to +1.05VS_PCH power for PCH ON OFF OFF Vcc 3.3V +/- 5%
+1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VSDGPU +1.5VS to +1.5VSDGPU switched power rail for GPU ON OFF OFF 0 0 0 V 0 V 0 V
+1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3VALW +3VALW always on power rail ON ON ON* 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3VALW_EC +3VALW always to KBC ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3V_LAN +3VALW to +3V_LAN power rail for LAN ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VALW_PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
2 2
+5VALW +5VALWP to +5VALW power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
+5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON*
BOARD ID Table BTO Option Table
+RTCVCC RTC power ON ON ON
BTO Item BOM Structure
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Board ID PCB Revision
UMA Only UMAO@
0 0.1
N12P-GS GS@
1 0.2
N12P-GV GV@
EC SM Bus1 address EC SM Bus2 address 2 0.3
Discrete(OPTIMUS) OPT@
3 1.0
VRAM X76@
Device Address Device Address 4
Smart Battery 0001 011X b
Blue Tooth BT@
5
AR8151 8151@
6
Connector CONN@
7
Unpop @
PCH SM Bus address
3 3
Device Address
Clock Generator (9LVS3199AKLFT,
Project ID Table USB Port Table
1101 0010b
RTM890N-631-VB-GRT) 3 External
DDR DIMM0 1001 000Xb
Project ID Project Name USB 2.0 USB 1.1 Port USB Port
DDR DIMM2 1001 010Xb
0 P3LJ0
0 USB/B (Right Side)
1 P4LJ0 UHCI0
1 USB/B (Right Side)
2 P5LJ0
2
3 P3LS0 UHCI1
3
4 P4LS0 EHCI1
4
5 P5LS0 UHCI2
5
6
6
7 UHCI3
7
8 Mini Card(WLAN)
UHCI4
9 Mini Card(WWAN)
10 Camera
EHCI2 UHCI5
11
4 4
12 SIM Card
UHCI6
13 Blue Tooth
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2010/09/28 Deciphered Date 2011/09/28 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB LA-7231P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019BL
Date: Friday, March 04, 2011 Sheet 3 of 57
A B C D E
5 4 3 2 1
D D
PEG_ICOMPI and RCOMPO signals should
be shorted and routed
with - max length = 500 mils - typical
+1.05VS_VCCP impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
1
R1 - typical impedance = 14.5 mohms
24.9_0402_1%
JCPU1A
2
J22 PEG_COMP
PEG_ICOMPI
PEG_ICOMPO J21
15 DMI_CRX_PTX_N0 B27 DMI_RX#[0] PEG_RCOMPO H22
15 DMI_CRX_PTX_N1 B25 DMI_RX#[1]
15 DMI_CRX_PTX_N2 A25 DMI_RX#[2]
15 DMI_CRX_PTX_N3 B24 K33 PEG_GTX_C_HRX_N15
DMI_RX#[3] PEG_RX#[0] PEG_GTX_C_HRX_N14
PEG_RX#[1] M35
15 DMI_CRX_PTX_P0 B28 L34 PEG_GTX_C_HRX_N13
DMI_RX[0] PEG_RX#[2] PEG_GTX_C_HRX_N12
15 DMI_CRX_PTX_P1 B26 DMI_RX[1] PEG_RX#[3] J35
15 DMI_CRX_PTX_P2 A24 J32 PEG_GTX_C_HRX_N11
DMI
DMI_RX[2] PEG_RX#[4] PEG_GTX_C_HRX_N10
15 DMI_CRX_PTX_P3 B23 DMI_RX[3] PEG_RX#[5] H34
H31 PEG_GTX_C_HRX_N9
PEG_RX#[6] PEG_GTX_C_HRX_N8
15 DMI_CTX_PRX_N0 G21 DMI_TX#[0] PEG_RX#[7] G33
E22 G30 PEG_GTX_C_HRX_N7
15 DMI_CTX_PRX_N1 DMI_TX#[1] PEG_RX#[8]
F21 F35 PEG_GTX_C_HRX_N6
15 DMI_CTX_PRX_N2 DMI_TX#[2] PEG_RX#[9]
D21 E34 PEG_GTX_C_HRX_N5
15 DMI_CTX_PRX_N3 DMI_TX#[3] PEG_RX#[10] PEG_GTX_C_HRX_N[0..15] 22
E32 PEG_GTX_C_HRX_N4
PEG_RX#[11] PEG_GTX_C_HRX_P[0..15] 22
G22 D33 PEG_GTX_C_HRX_N3
15 DMI_CTX_PRX_P0 DMI_TX[0] PEG_RX#[12]
D22 D31 PEG_GTX_C_HRX_N2
C 15 DMI_CTX_PRX_P1 DMI_TX[1] PEG_RX#[13] PEG_HTX_C_GRX_N[0..15] 22 C
F20 B33 PEG_GTX_C_HRX_N1
PCI EXPRESS* - GRAPHICS
15 DMI_CTX_PRX_P2 DMI_TX[2] PEG_RX#[14] PEG_HTX_C_GRX_P[0..15] 22
C21 C32 PEG_GTX_C_HRX_N0
15 DMI_CTX_PRX_P3 DMI_TX[3] PEG_RX#[15]
J33 PEG_GTX_C_HRX_P15
PEG_RX[0] PEG_GTX_C_HRX_P14
PEG_RX[1] L35
K34 PEG_GTX_C_HRX_P13
PEG_RX[2] PEG_GTX_C_HRX_P12
15 FDI_CTX_PRX_N0 A21 FDI0_TX#[0] PEG_RX[3] H35
H19 H32 PEG_GTX_C_HRX_P11
15 FDI_CTX_PRX_N1 FDI0_TX#[1] PEG_RX[4]
E19 G34 PEG_GTX_C_HRX_P10
15 FDI_CTX_PRX_N2 FDI0_TX#[2] PEG_RX[5]
F18 G31 PEG_GTX_C_HRX_P9
15 FDI_CTX_PRX_N3 FDI0_TX#[3] PEG_RX[6]
Intel(R) FDI
B21 F33 PEG_GTX_C_HRX_P8
15 FDI_CTX_PRX_N4 FDI1_TX#[0] PEG_RX[7]
C20 F30 PEG_GTX_C_HRX_P7
15 FDI_CTX_PRX_N5 FDI1_TX#[1] PEG_RX[8]
D18 E35 PEG_GTX_C_HRX_P6
15 FDI_CTX_PRX_N6 FDI1_TX#[2] PEG_RX[9]
E17 E33 PEG_GTX_C_HRX_P5
15 FDI_CTX_PRX_N7 FDI1_TX#[3] PEG_RX[10]
F32 PEG_GTX_C_HRX_P4
PEG_RX[11] PEG_GTX_C_HRX_P3
PEG_RX[12] D34
A22 E31 PEG_GTX_C_HRX_P2
15 FDI_CTX_PRX_P0 FDI0_TX[0] PEG_RX[13]
G19 C33 PEG_GTX_C_HRX_P1
15 FDI_CTX_PRX_P1 FDI0_TX[1] PEG_RX[14]
E20 B32 PEG_GTX_C_HRX_P0
15 FDI_CTX_PRX_P2 FDI0_TX[2] PEG_RX[15]
15 FDI_CTX_PRX_P3 G18 FDI0_TX[3]
B20 M29 PEG_HTX_GRX_N15 C1 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N15
15 FDI_CTX_PRX_P4 FDI1_TX[0] PEG_TX#[0]
C19 M32 PEG_HTX_GRX_N14 C2 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N14
15 FDI_CTX_PRX_P5 FDI1_TX[1] PEG_TX#[1]
D19 M31 PEG_HTX_GRX_N13 C3 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N13
15 FDI_CTX_PRX_P6 FDI1_TX[2] PEG_TX#[2]
F17 L32 PEG_HTX_GRX_N12 C4 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N12
15 FDI_CTX_PRX_P7 FDI1_TX[3] PEG_TX#[3]
L29 PEG_HTX_GRX_N11 C5 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N11
+1.05VS_VCCP PEG_TX#[4] PEG_HTX_GRX_N10 C6 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N10
15 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#[5] K31 1 2
15 FDI_FSYNC1 J17 K28 PEG_HTX_GRX_N9 C7 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N9
FDI1_FSYNC PEG_TX#[6] PEG_HTX_GRX_N8 C8 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N8
PEG_TX#[7] J30 1 2
15 FDI_INT H20 J28 PEG_HTX_GRX_N7 C9 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N7
FDI_INT PEG_TX#[8] PEG_HTX_GRX_N6 C10 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N6
eDP_COMPIO and ICOMPO signals PEG_TX#[9] H29 1 2
1
15 FDI_LSYNC0 J19 G27 PEG_HTX_GRX_N5 C11 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N5
should be shorted near balls R2 H17
FDI0_LSYNC PEG_TX#[10]
E29 PEG_HTX_GRX_N4 C12 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N4
15 FDI_LSYNC1 FDI1_LSYNC PEG_TX#[11]
B and routed with typical 24.9_0402_1%
PEG_TX#[12] F27 PEG_HTX_GRX_N3 C13 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N3 B
D28 PEG_HTX_GRX_N2 C14 1 2 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N2
impedance <25 mohms PEG_TX#[13] PEG_HTX_GRX_N1 C15 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N1
F26 1 2
2
PEG_TX#[14] PEG_HTX_GRX_N0 C16 OPT@ 0.1U_0402_10V7K PEG_HTX_C_GRX_N0
PEG_TX#[15] E25 1 2
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