Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 5020_Wistron_Bolsena_Rev-1
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5 4 3 2 1
See 'TEXT' in 0MEMO or 1MEMO property in component
Dummy when 'USE EZ4'
Dummy when 'NO EZ4' Bolsena Block Diagram 91.4C501.001 (04243)
Dummy when use '10/100' 200-PIN DDR SODIMM
Dummy when use 'GIGA' CLK GEN AMD CPU DDR 333/400
IDT CV1373 DDR x2
Dummy when use 'UMA' 35W/25W
D D
Dummy when use 'DIS' 8,9,10
LEDs 17
Dummy when use 'SATA' 4,5,6,7
RTC BAT. 18
Dummy when use 'IDE'
BUTTONs 35 SVIDEO/COMP
HyperTransport TVOUT 16
Dummy when use ''M26'
6.4GB/S 16b/8b
Dummy when use ''M24'
LVDS
PWR SW ATI LCD 17
TSP2220A RS480M Power Block Diag -> Page 40
28
TI
PCMCIA AGTL+ CPU I/F + UMA
PCI 7411
SLOT PCI Express x16 ATI
PCMCIA I/F 1* Slot Cardbus 11,12,13,14 RGB CRT
Support 1* 1394 M26/M24 CRT 16
TypeII CardReader 50,51,52
C
28 MS/xD CH7301C 15 C
SM/MMC/SD PCI-Express
1394 4pin 5 in 1 28 x2 VRAM x4 TMDS DVI-D
Conn 28 26,27 (M26/M24 diff.) 53,54 (EZ4 only ) 15
ATI BlueTooth
SB400 miniUSB
Mini-PCI PCI Bus / 33MHz 24
ACPI 2.0 6xUSB 2.0
USB x 4
802.11a/b/g PCI 24
31 CODEC Line In 33
AC97 ALC655 MIC In
32
6-CH
1000Mb AC97 2.2
RJ45 TXFM PCI LAN Line Out33
30 30
MODEM RJ11
Realtek OP AMP
MDC Card CONN
RTL8110SBL 30 G1421
24 33
1000/100/10 Int. SPKR33
TXFM 10/100Mb
B
RTL8100C B
30
100/10 29 LPC Bus / 33MHz
LPC I/F
ATA 133 18,19,20,21,22
Thermal XBUS
NS SIO KBC
& Fan
PIDE
SIDE
PC87392 KB3910
37
G792 23 34
DVD/
SATA HDD
CD-RW
25 25 25 Touch Int.
ISA ROM
Pad KB
FIR 35 35 36
37
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Port Replicator 4 (124 PIN) Taipei Hsien 221, Taiwan, R.O.C.
Title
AC RJ45-11 SEARIAL PRINTER PS2 MIC LINE IN LINE TV DVI PCIeX2 SMBUS BLOCK DIAGRAM
IN PORT CRT OUT OUT Size
A3
Document Number Rev
-1
Bolsena
Date: Tuesday, April 12, 2005 Sheet 1 of 58
5 4 3 2 1
5 4 3 2 1
PCI Routing
IDSEL IRQ REQ/GNT
MiniPCI 21 F 0
LAN 23 H 2
D D
7411 22 E (CardBus) 1
7411 22 G (1394) 1
7411 22 E (FlashMedia) 1
C C
B B
Ref. function schematic BOM
-------------------------
U81 cpu socket 62.10055.091 (DON'T CHANGE) (3mm high)
U80 north bridge 71.RS48M.00U 71.RS48M.B0U (ver A22)
U43 south bridge 71.SB400.B0U 71.SB400.D0U (ver A32)
U32 clock gen. 71.00137.A0W 71.00137.B0W
---
U70 VGA M24 71.0M26P.00U 71.00M24.C0U
U64 VRAM FOR M24 72.55732.B0U 72.52832.E05
U65 VRAM FOR M24 72.55732.B0U 72.52832.E05
U69 VRAM FOR M24 72.55732.B0U 72.52832.E05
U71 VRAM FOR M24 72.55732.B0U 72.52832.E05
---
U70 VGA M26 71.0M26P.00U (DON'T CHANGE)
U64 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
U65 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
U69 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
U71 VRAM FOR M26 72.55732.B0U (DON'T CHANGE)
---
U66 BIOS SOCKET 72.39040.G03 62.10002.032 (NO NEED WHEN PD)
U66 BIOS IC 72.39040.G03 72.39040.H03 (DIP STAGE IN LAB, SMT IN PD)
A --- A
LOUT1 AUDIO 22.10257.001 22.10147.031 (NO SPDIF)
---
U75 GIGA LAN 71.08110.00G 71.08110.A0G Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
U75 10/100 LAN 71.08110.00G 71.08100.C0G Taipei Hsien 221, Taiwan, R.O.C.
---
HDD1 20.80175.044 20.80592.044 Title
SATA1 20.F0614.022 20.F0665.022 CHANGE HISTORY
EZ4 20.80579.120 20.80591.120 (AFTER SB) Size Document Number Rev
A3 Bolsena -1
Date: Thursday, March 31, 2005 Sheet 2 of 58
5 4 3 2 1
A B C D E
3D3V_S0
3D3V_S0 3D3V_CLK_VDD 3D3V_CLK_VDDA
1 L14 2 1 L12 2
0R0603-PAD 0R0603-PAD
1
1
1
1
1
1
1
SC 0308
C421 C423 C397 C398 C415 C418 C414
SC 0308 SCD1U16V SCD1U16V SCD1U16V SCD1U16V SC10U10V5ZY SCD1U16V SC10U10V5ZY
2
2
2
2
2
2
2
RN56
2 3 SRN33-2-U2 SBLINK_CLK# 13
3D3V_CLK_VDDA 1 4 SBLINK_CLK 13
1
1
1
1
4 1 4 RN45 SBSRC_CLK# 18 4
C416 C417 C420 C419 3D3V_S0 3D3V_CLK_VDD 2 3 SBSRC_CLK 18
SCD1U16V SCD1U16V SCD1U16V SCD1U16V U32 SRN33-2-U2
2
2
2
2
1 L13 2 3D3VDD48_S0 3 33 SRC_CLK0# RN46
0R0603-PAD VDD_48 SRCC0 SRC_CLK0
39 VDDA SRCT0 34 1 4 CLK_PCIE_DOCK1# 57
1
32 25 SRC_CLK3# 2 3 CLK_PCIE_DOCK1 57
SC 0308 C399 VDD_SRC SRCC3 SRC_CLK3
SRCT3 24
SC2D2U16V5ZY 21 23 SRC_CLK4# SRN33-2-U2
2
VDD_SRC SRCC4 SRC_CLK4
14 22 RN47
VDD_SRC SRCT4 SRC_CLK5#
35 VDD_SRC SRCC5 19 1 4 CLK_PCIE_DOCK2# 57
18 SRC_CLK5 2 3 CLK_PCIE_DOCK2 57
SRCT5
56 VDD_REF SRCC6 17
51 16 SRN33-2-U2
VDD_PC1 SRCT6
1 2 C400 XI_CLK 43 VDD_CPU SRCC7 13 Dummy when no EZ4
Dummy when 'NO EZ4' SC33P50V2JN 48 VDD_HTT SRCT7 12
1
2
R278 40
57 SMBC_SB_EZ4 X2 DUMMY-R3 CPUC1
57 SMBD_SB_EZ4 1 XIN CPUT1 41
X-14D318MHZ-1-U1 2 44 CPUCLKJ_CY 1 R296 2 15R2J CPUCLK# 6
XOUT CPUC0 CPUCLK_CY
45 1 R297 2 15R2J CPUCLK 6
1
CPUT0
2
1
USB_48M 4
2
RN120 USB_48
1 2 C422 XO_CLK SMBC_CLK 7 SCL
RN55
SC33P50V2JN SMBD_CLK 8 29 ATI_CLK0# 2 3 NBSRC_CLK# 13
SRN33-2-U2 R264 2 22R2 SDA SRCC1 ATI_CLK0
26 CLK48_CARDBUS 1 SRCT1 30 1 4 NBSRC_CLK 13
1 R263 2 22R2 10 28 ATI_CLK1#
21 CLK48_USB CLKREQ0# SRCC2 ATI_CLK1
11 27 SRN33-2-U2
3
4
R261 CLKREQ1# SRCT2
8,21 SMBC_SB 1 2 33R2
1 2 RN44 CLK_PCIE_DOCK1# 1 R253 2
3 8,21 SMBD_SB R260 33R2 SC 0309 FS2 49D9R2F 3
9 SEL24/24_48# VSS_SRC 36 1 4 GFX_CLK# 49
SC 0309 1 R277 2 FS1 53 20 2 3 CLK_PCIE_DOCK1 1 R254 2
13 CLK14_NB REF1 VSS_SRC GFX_CLK 49
1 R279 2 33R2 FS0 54 15 49D9R2F
21 SB_OSC_CLK 33R2 REF0 RESET# CLK_PCIE_DOCK2#
TURBO1 26 SRN33-2-U2 1 R255 2
1 R274 2 CLK_REF2 52 49D9R2F
37 CLK14_SIO REF2
R280 13 HTREF_CLK R273 2
33R2
CLK_HTT66 47 VSS_CPU 42 Dummy when use UMA CLK_PCIE_DOCK2 1 R256 2
49D9R2F
32 CLK14_AUDIO 1 2 1 HTT66 VSS_PCI 49
33R2 75R2F 50 PCI0 VSS_HTT 46
SBLINK_CLK#
Dummy when no EZ4
R294
VSS_SRC 31 1 2
IREF_CLKGEN 37 38 49D9R2F
IREF VSSA SBLINK_CLK
1 VSS_48 5 1 R295 2
1
6 55 49D9R2F
R298 R272 NC#6 VSS_REF SBSRC_CLK# 1 R251 2
100R2F 475R2F 49D9R2F
IDTCV137PAG SBSRC_CLK 1 R252 2
CHANGE TO 71.00137.B0W 49D9R2F
2
2
GFX_CLK# 1 R249 2
49D9R2F
GFX_CLK 1 R250 2
SB 0219 49D9R2F
Dummy when use UMA
2 2
NBSRC_CLK# 1 R292 2
49D9R2F
NBSRC_CLK 1 R293 2
49D9R2F
3D3V_CLK_VDD
DY
1 R281 2 FS0
2K2R2
1 2
DUMMY-R2
R299
1 R275 2 DY FS1
2K2R2
1 2
DUMMY-R2
R276
1 1
1 R257 2 DY FS2
2K2R2
1 2 Wistron Corporation
DUMMY-R2 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
R258 Taipei Hsien 221, Taiwan, R.O.C.
for ICS
Title
CLKGEN_IDTCV137
Size Document Number Rev
A3 -1
Bolsena
Date: Thursday, March 31, 2005 Sheet 3 of 58
A B C D E
A B C D E
4 4
HTT for CPU sideA HTT for CPU sideB
Transmit power Receive power
and NB sideA Receive and NB sideA
power Transmit power
1D2V_S0 U81A 1D2V_HT0B_S0
D29 VLDT0_A VLDT0_B AH29 LAYOUT: Place bypass cap on topside of board near
D27 AH27
VLDT0_A VLDT0_B HTT power pins that are not connected directly to
1
1
1
1
1
D25 VLDT0_A VLDT0_B AG28
3 C244 C245 C246 C247 C28 AG26 C242 downstream HTT device, but connected internally to 3
SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY SCD22U16V3ZY VLDT0_A VLDT0_B SC4D7U10V5ZY
C26 AF29
other HTT power pins.
2
2
2
2
2
VLDT0_A VLDT0_B
B29 VLDT0_A VLDT0_B AE28
B27 VLDT0_A VLDT0_B AF25
NB0CADOUT15 T25 N26 CPUCADOUT15 CPUCADOUT[15..0] 11
11 NB0CADOUT[15..0] NB0CADOUTJ15 L0_CADIN_H15 L0_CADOUT_H15 CPUCADOUTJ15
11 NB0CADOUTJ[15..0] R25 L0_CADIN_L15 L0_CADOUT_L15 N27 CPUCADOUTJ[15..0] 11
NB0CADOUT14 U27 L25 CPUCADOUT14
NB0CADOUTJ14 L0_CADIN_H14 L0_CADOUT_H14 CPUCADOUTJ14
U26 L0_CADIN_L14 L0_CADOUT_L14 M25
Used SideB Power Plane NB0CADOUT13 V25 L26 CPUCADOUT13 Used SideA Power Plane
NB0CADOUTJ13 L0_CADIN_H13 L0_CADOUT_H13 CPUCADOUTJ13
U25 L0_CADIN_L13 L0_CADOUT_L13 L27
NB0CADOUT12 W27 J25 CPUCADOUT12
NB0CADOUTJ12 L0_CADIN_H12 L0_CADOUT_H12 CPUCADOUTJ12
W26 L0_CADIN_L12 L0_CADOUT_L12 K25
NB0CADOUT11 AA27 G25 CPUCADOUT11
NB0CADOUTJ11 L0_CADIN_H11 L0_CADOUT_H11 CPUCADOUTJ11
AA26 L0_CADIN_L11 L0_CADOUT_L11 H25
NB0CADOUT10 AB25 G26 CPUCADOUT10
NB0CADOUTJ10 L0_CADIN_H10 L0_CADOUT_H10 CPUCADOUTJ10
AA25 L0_CADIN_L10 L0_CADOUT_L10 G27
NB0CADOUT9 AC27 E25 CPUCADOUT9
NB0CADOUTJ9 L0_CADIN_H9 L0_CADOUT_H9 CPUCADOUTJ9
AC26 L0_CADIN_L9 L0_CADOUT_L9 F25
NB0CADOUT8 AD25 E26 CPUCADOUT8
NB0CADOUTJ8 L0_CADIN_H8 L0_CADOUT_H8 CPUCADOUTJ8
AC25 L0_CADIN_L8 L0_CADOUT_L8 E27
NB0CADOUT7 T27 N29 CPUCADOUT7
NB0CADOUTJ7 L0_CADIN_H7 L0_CADOUT_H7 CPUCADOUTJ7
T28 L0_CADIN_L7 L0_CADOUT_L7 P29
NB0CADOUT6 V29 M28 CPUCADOUT6
NB0CADOUTJ6 L0_CADIN_H6 L0_CADOUT_H6 CPUCADOUTJ6
U29 L0_CADIN_L6 L0_CADOUT_L6 M27
NB0CADOUT5 V27 L29 CPUCADOUT5
NB0CADOUTJ5 L0_CADIN_H5 L0_CADOUT_H5 CPUCADOUTJ5
V28 L0_CADIN_L5 L0_CADOUT_L5 M29
NB0CADOUT4 Y29 K28 CPUCADOUT4
NB0CADOUTJ4 L0_CADIN_H4 L0_CADOUT_H4 CPUCADOUTJ4
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