Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 5542_Wistron_JV50-TR_8VRAM_JV50-TR8_Rev-1
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5 4 3 2 1
Project code: 91.4FN01.001
JV50-TR_8VRAM Block Diagram PCB P/N : 48.4FN02.001
REVISION : 09927-1
PCB STACKUP
DDR2 667/800MHz
TOP
SYSTEM DC/DC
D 667/800 MHz AMD Caspian CPU G792 RT8205A 46 D
16,17 INPUTS OUTPUTS
S1G3 (35W) 35 CRT VCC
5V_S5(6A)
DCBATOUT
20
DDR2 667/800MHz
638-Pin uFCPGA638
4,5,6,7
S 3D3V_S5(6A)
667/800 MHz LCD S SYSTEM DC/DC
16,17 19 GND TPS51124 47
INPUTS OUTPUTS
OUT
HDMI BOTTOM 1D1V_S0(7.5A)
IN
16X16 DCBATOUT
21 1D2V_S0(4A)
16X
VRAM SYSTEM DC/DC
North Bridge Madison
CLK GEN. 3 AMD RS880M
55,56,57,58,59 DDR3
60,61,62,63
RT8209B
INPUTS
48
OUTPUTS
ICS9LPRS480BKLFT 71.09480.A03 CPU I/F LVDS, CRT I/F
RTM880N-796-VB-GRT 71.00880.A03 DCBATOUT 1D8V_S3(11A)
INTEGRATED GRAHPICS LAN
Giga LAN TXFM RJ45 G9661 49
27 27
C
BCM5784 26 5V_S5 1D1V_M92 C
INT MIC 8,9,10
New card PWR SW DY RT9161 49
30 DY W83L351YG
34 28 3D3V_S0 2D5V_S0
A-Link PCIex1 (200mA)
Line In Codec AZALIA 4X4 Mini Card G957 49
30
ALC888S WLAN 33
3D3V_S0 1D5V_S0
28 (1A)
MIC In Mini Card
South Bridge DY 33 G9161 49
30 AMD SB710
LPC BUS
3D3V_S5 1D2V_S5
(400mA)
INT.SPKR USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb) BIOS CHARGER
30 OP AMP High Definition Audio KBC
MXIC
MX25L1605
LPC MAX8731 50
MAX9789
29 ATA 66/100 Winbond 37 DEBUG INPUTS OUTPUTS
WPC773 CONN.37
B 36 B
Line Out CHG_PWR
ACPI 1.1
(SPDIF) 18V 6.0A
LPC I/F DCBATOUT
UP+5V
30 Touch INT. 5V 100mA
PCI/PCI BRIDGE
11,12,13,14,15 Pad 38 KB 36 Daughter Board
Finger Printer Board CPU DC/DC
ISL6265AHR 45
08650-1
MODEM SATA USB INPUTS OUTPUTS
CardReader VCC_CORE_S0_0
RJ11 MDC Card MS/MS Pro/xD
31 Realtek 0~1.55V 18A
Mini USB /MMC/SD
RTS5159 32 5 in 1
32 VCC_CORE_S0_1
Blue Tooth 24 Daughter Board DCBATOUT
HDD SATA 0~1.55V 18A
Mini sensor Board
22 VDDNB
USB 08696-1 0~1.55V 18A
2 Port 25
ODD SATA
Finger
A 23 JV50-TR8 A
Printer 31
Camera Daughter Board Daughter Board
USB Board LED Board Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
08649-1 08651-1
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
JV50-TR8 -1
Date: Monday, October 05, 2009 Sheet 1 of 63
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
JV50-TR8
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
USB/PCIE Routing
Size Document Number Rev
A3
JV50-TR8 -1
Date: Monday, October 05, 2009 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
3D3V_S0
1 R215 2 R221
0R0603-PAD 1 2 3D3V_48MPW R_S0
1
1
1
1
1
1
1
1
1
C500 C501 DY C502 C467 C453 C476 C462 C492 C504 Due to PLL issue on current clock chip, the SBlink clock
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
DY 2R3J-GP C511 C506
SC1U10V2KX-1GP need to come from SRC clocks for RS740 and RS780.
DY
2
2
2
2
2
2
2
2
2
SC4D7U6D3V3KX-GP
SC4D7U6D3V3KX-GP
Future clock chip revision will fix this.
2
2
3000mA.80ohm
D D
Clock chip has internal serial terminations
3D3V_S0 for differencial pairs, external resistors are
reserved for debug purpose.
1 R197 2
0R0603-PAD
1D1V_CLK_VDDIO C508
SC39P50V2JN-1GP
R218
1 DY 2 1 2
1
1
1
1
1
1
1
C459 C460 C454 C461 C472 C464 C495 3D3V_CLK_VDD X5
1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
10MR2J-L-GP X-14D31818M-35GP
U20 82.30005.891
2
2
2
2
2
2
2
1D1V_CLK_VDDIO C509 2ND = 82.30005.951 SB
26 61 GEN_XTAL_IN
2
VDDATIG X1 GEN_XTAL_OUT
25 VDDATIG_IO X2 62 1 2
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