Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 5553_Quanta_ZR8_Rev1A
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SGN@---->Internal CLK GEN.
GN@ ---->External CLK GEN.
IV@ -----> iGPU
ZR8 SYSTEM DIAGRAM
SW@ -----> dGPU
DDR3-SODIMM1 DDR3 channel A
SP@ -----> iGPU & dGPU notice CPU THERMAL
SPE@ ----->Only for dGPU notice AMD Champlain
SIDE@ ----> Side port
P5
35mm X 35mm
SENSOR
A A
S1G4 Processor P4
DDR3-SODIMM2 DDR3 channel B
638P (PGA)45W/35W
P6 P2 ~ 4 CPU_CLK
NBGFX_CLK CLOCK GEN
NBGPP_CLK
SBLINK_CLK P11
HT3
PCI-E
P25
NORTH BRIDGE 29mm X 29mm
P24
RS880
P16 ~ 20
A12 P7
P24
B P24 B
(10/100/1000)
P26 P27
P7 ~ 10
P22,23
ALINK X4
P26
Charger (ISL88731A)
P35 P28 SOUTH BRIDGE P31
DC/DC ( 3VPCU / 5VPCU ) SB820
RT8206B P36 P28
4.5W(Ext)
C CPU_VCORE ( VCORE ) 4.3W(Int) C
ISL6265A P37
DC/DC ( +1.1V_S5 ) P11 ~ 14
P31 P24
UP6111AQD P38
P30
DC/DC ( NB_CORE )
UP6111AQD P39
DC/DC ( +1.5VSUS )
RT8207A P40
P31
P29
P34
DC/DC ( GPU_CORE )
MAX8792ETD+T P41
D
DC/DC (+1.8V/+1V/+2.5V ) D
HPA00835RTER / RT9018A / RT9025-25PSP P42
P33
DC/DC ( CPU_VDDR ) P31 P33 P34 P24 P29 P29
RT9025-25PSP P43
Size Document Number Rev
Block Diagram 1A
Date: Wednesday, May 27, 2009 Sheet 1 of 49
1 2 3 4 5 6 7 8
5 4 3 2 1
W/S= 15 mil/20mil SB check list tide to CPUVDDIO (+1.5VSUS)
03
+2.5V L40 +CPUVDDA
PBY201209T-221Y-N CPU_PWRGD_SVID_REG 300/F_4 R236
2.5V@250mA CPU_LDT_RST# 300/F_4 R261
+1.1V [email protected] +1.1V_VLDT C447
4.7u/6.3V_6
C436
4.7u/6.3V_6
C428
0.22u/6.3V_4
C432
3300P/50V_4
C440
[11] CLK_CPU_BCLKP_PR
CLK_CPU_BCLKP_PR
CLK_CPU_BCLKN_PR
CPU_LDT_STOP#
CPU_LDT_REQ#_CPU
300/F_4
*300/F_4
R249
R463
+1.5V
A41 *10U/6.3V_8 [11] CLK_CPU_BCLKN_PR
R124 *SHORT_PAD
Keep trace from resisor to CPU within 0.6"
R121 *SHORT_PAD +CPUVDDA 250mA
keep trace from caps to CPU within 1.2" U29D
U29A W/S= 15 mil/20mil
P/N: DG0^8000004 CLK_CPU_BCLKP_C R464 169/F_4 CLK_CPU_BCLKN_C +CPUVDDA F8 VDDA1 VSS M11 S1G4
DG0^8000005 C414 10U/6.3V_8 +1.1V_VLDT D1 VLDT_A0 HT LINK VLDT_B0 AE2 +1.1V_VLDT 10U/6.3V_8 C397 +CPUVDDA F9 VDDA2 RSVD11 W 18
C265 10U/6.3V_8 +1.1V_VLDT D2 AE3 +1.1V_VLDT 0.22u/6.3V_4 C273
D DG0^8000009 C376 0.22u/6.3V_4 +1.1V_VLDT D3
VLDT_A1 VLDT_B1
AE4 +1.1V_VLDT 180P/50V_4 C387 CLK_CPU_BCLKP_PR C704 3900P/25V_4 CLK_CPU_BCLKP_C A9 A6 CPU_SVC D
C274 180P/50V_4 +1.1V_VLDT VLDT_A2 VLDT_B2 +1.1V_VLDT CLK_CPU_BCLKN_PR C703 3900P/25V_4 CLK_CPU_BCLKN_C CLKIN_H SVC CPU_SVD
DG0^80000013 D4 VLDT_A3 VLDT_B3 AE5 A8 CLKIN_L SVD A4
DG0^80000014 HT_CADINP0 E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUTP0
[11] CPU_LDT_RST#
CPU_LDT_RST# B7 RESET_L
HT_CADINN0 E2 AC1 HT_CADOUTN0 CPU_PWRGD_SVID_REG
A7
L0_CADIN_L0 L0_CADOUT_L0 [11,37] CPU_PWRGD_SVID_REG PW ROK
HT_CADINP1 E1 AC2 HT_CADOUTP1 CPU_LDT_STOP# F10 AF6 CPU_THERMTRIP_L#
L0_CADIN_H1 L0_CADOUT_H1 [9,11] CPU_LDT_STOP# LDTSTOP_L THERMTRIP_L
HT_CADINN1 F1 AC3 HT_CADOUTN1 CPU_LDT_REQ#_CPU C6 AC7 CPU_PROCHOT_L#
HT_CADINP2 L0_CADIN_L1 L0_CADOUT_L1 HT_CADOUTP2 LDTREQ_L PROCHOT_L CPU_MEMHOT_L#
G3 L0_CADIN_H2 L0_CADOUT_H2 AB1 MEMHOT_L AA8
HT_CADINN2 G2 AA1 HT_CADOUTN2 SideBand Temp sense I2C [4] AF4
HT_CADINP[15..0] L0_CADIN_L2 L0_CADOUT_L2 CPU_SIC SIC
HT_CADINP3 G1 AA2 HT_CADOUTP3 AF5
[7] HT_CADINP[15..0] L0_CADIN_H3 L0_CADOUT_H3 [4] CPU_SID SID
HT_CADINN3 H1 AA3 HT_CADOUTN3 AE6 W7
HT_CADINN[15..0] L0_CADIN_L3 L0_CADOUT_L3 [4] CPU_ALERT ALERT_L THERMDC H_THRMDC [4]
HT_CADINP4 J1 W2 HT_CADOUTP4 W8
[7] HT_CADINN[15..0] L0_CADIN_H4 L0_CADOUT_H4 THERMDA H_THRMDA [4]
HT_CADINN4 K1 W3 HT_CADOUTN4 R207 44.2/F_4 CPU_HTREF0 R6
HT_CLKINP[1..0] HT_CADINP5 L0_CADIN_L4 L0_CADOUT_L4 HT_CADOUTP5 R208 44.2/F_4 CPU_HTREF1 HT_REF0
[7] HT_CLKINP[1..0] L3 L0_CADIN_H5 L0_CADOUT_H5 V1 S1G4 +1.1V_VLDT P6 HT_REF1
HT_CADINN5 L2 U1 HT_CADOUTN5 place them to CPU within 1.5"
HT_CLKINN[1..0] HT_CADINP6 L0_CADIN_L5 L0_CADOUT_L5 HT_CADOUTP6 VDDIO_FB_H
L1 L0_CADIN_H6 L0_CADOUT_H6 U2 [37] CPU_VDD0_FB_H F6 VDD0_FB_H VDDIO_FB_H W9 VDDIO_FB_H [40]
[7] HT_CLKINN[1..0] HT_CADINN6 HT_CADOUTN6 VDDIO_FB_L
M1 L0_CADIN_L6 L0_CADOUT_L6 U3 [37] CPU_VDD0_FB_L E6 VDD0_FB_L VDDIO_FB_L Y9 VDDIO_FB_L [40]
HT_CTLINP[1..0] HT_CADINP7 N3 T1 HT_CADOUTP7
[7] HT_CTLINP[1..0] HT_CADINN7 L0_CADIN_H7 L0_CADOUT_H7 HT_CADOUTN7
N2 L0_CADIN_L7 L0_CADOUT_L7 R1 [37] CPU_VDD1_FB_H Y6 VDD1_FB_H VDDNB_FB_H H6 CPU_VDDNB_FB_H [37]
HT_CTLINN[1..0] HT_CADINP8 E5 AD4 HT_CADOUTP8 AB6 G6
[7] HT_CTLINN[1..0] L0_CADIN_H8 L0_CADOUT_H8 [37] CPU_VDD1_FB_L VDD1_FB_L VDDNB_FB_L CPU_VDDNB_FB_L [37]
HT_CADINN8 F5 AD3 HT_CADOUTN8
HT_CADOUTP[15..0] HT_CADINP9 L0_CADIN_L8 L0_CADOUT_L8 HT_CADOUTP9 CPU_DBRDY
[7] HT_CADOUTP[15..0]
F3 L0_CADIN_H9 L0_CADOUT_H9 AD5 G10 DBRDY
HT_CADINN9 F4 AC5 HT_CADOUTN9 CPU_TMS AA9 E10 CPU_DBREQ# R247 *300/F_4
L0_CADIN_L9 L0_CADOUT_L9 TMS DBREQ_L +1.5V
HT_CADOUTN[15..0] HT_CADINP10 G5 AB4 HT_CADOUTP10 CPU_TCK AC9 R246 300/F_4
[7] HT_CADOUTN[15..0] L0_CADIN_H10 L0_CADOUT_H10 TCK +1.5VSUS
HT_CADINN10 H5 AB3 HT_CADOUTN10 CPU_TRST# AD9 AE9 CPU_TDO
HT_CLKOUTP[1..0] HT_CADINP11 L0_CADIN_L10 L0_CADOUT_L10 HT_CADOUTP11 CPU_TDI TRST_L TDO
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 AF9 TDI
[7] HT_CLKOUTP[1..0] HT_CADINN11 HT_CADOUTN11
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 PV stage:add +1.8VSUS option R3114
HT_CLKOUTN[1..0] HT_CADINP12 K3 Y5 HT_CADOUTP12 CPUTEST23 AD7 J7
[7] HT_CLKOUTN[1..0] L0_CADIN_H12 L0_CADOUT_H12 TEST23 TEST28_H for Caspian CPU power leakage issue
HT_CADINN12 K4 W5 HT_CADOUTN12 H8
HT_CTLOUTP[1..0] HT_CADINP13 L0_CADIN_L12 L0_CADOUT_L12 HT_CADOUTP13 CPUTEST18 TEST28_L
L5 L0_CADIN_H13 L0_CADOUT_H13 V4 H10 TEST18
C [7] HT_CTLOUTP[1..0] HT_CADINN13 HT_CADOUTN13 CPUTEST19 CPUTEST17 C
M5 L0_CADIN_L13 L0_CADOUT_L13 V3 G9 TEST19 TEST17 D7 T28
HT_CTLOUTN[1..0] HT_CADINP14 M3 V5 HT_CADOUTP14 E7 CPUTEST16
[7] HT_CTLOUTN[1..0] HT_CADINN14 L0_CADIN_H14 L0_CADOUT_H14 HT_CADOUTN14 CPUTEST25H TEST16 CPUTEST15 T27
M4 U5 +1.5VSUS R245 510/F_4 E9 F7
L0_CADIN_L14 L0_CADOUT_L14 TEST25_H TEST15 T26
HT_CADINP15 N5 T4 HT_CADOUTP15 R241 510/F_4 CPUTEST25L E8 C7 CPUTEST14
L0_CADIN_H15 L0_CADOUT_H15 TEST25_L TEST14 T29
HT_CADINN15 P5 T3 HT_CADOUTN15 place them to CPU within 1.5"
L0_CADIN_L15 L0_CADOUT_L15 CPUTEST21 AB8 TEST21 TEST7 C3
HT_CLKINP0 J3 Y1 HT_CLKOUTP0 CPUTEST20 AF7 K8
HT_CLKINN0 L0_CLKIN_H0 L0_CLKOUT_H0 HT_CLKOUTN0 CPUTEST24 TEST20 TEST10
J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 AE7 TEST24
HT_CLKINP1 J5 Y4 HT_CLKOUTP1 CPUTEST22 AE8 C4
HT_CLKINN1 L0_CLKIN_H1 L0_CLKOUT_H1 HT_CLKOUTN1 CPUTEST12 TEST22 TEST8
K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 AC8 TEST12
R422 1K/F_4 CPUTEST27 AF8
+1.5VSUS TEST27
HT_CTLINP0 N1 R2 HT_CTLOUTP0 C9 CPUTEST29H
HT_CTLINN0 L0_CTLIN_H0 L0_CTLOUT_H0 HT_CTLOUTN0 TEST29_H T30
P1 R3 R430 *300/F_4 C2 C8
HT_CTLINP1 L0_CTLIN_L0 L0_CTLOUT_L0 HT_CTLOUTP1 TEST9 TEST29_L
P3 L0_CTLIN_H1 L0_CTLOUT_H1 T5 AA6 TEST6
HT_CTLINN1 P4 R5 HT_CTLOUTN1 R250
L0_CTLIN_L1 L0_CTLOUT_L1
A3 RSVD1 RSVD10 H18 80.6/F_4
FOX PZ63826-284R-41F A5 RSVD2 RSVD9 H19
DG0^8000004 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN B3 AA7 CPUTEST29L
RSVD3 RSVD8 T31
+1.5VSUS B5 D5
MLX 47296-4131 [3,4,5,6,37,40,42,43,44,46] +1.5VSUS RSVD4 RSVD7
+1.5V C1 C5
DG0^8000003 IC SOCKET SMD 638P S1(P1.27,H3.2) [7,10,27,29,40,43] +1.5V RSVD5 RSVD6
+1.1V
[7,8,9,10,14,38,44] +1.1V
TYC 4-1903401-2 +2.5V S1G4
[42] +2.5V
DG0^8000005 IC SOCKET SMD 638P S1(P1.27,H3.2) SOCKET_638_PIN
CNTR_VREF [4] +3V
C446 0.1u/10V_4
S1G4 Serial VID VFIX MODE VID Override Circuit
+3V R256 20K/F_4 R251 34.8K/F_4
B R262 B
CNTR_VREF
SVC SVD Voltage Output
4.7K_4
0 0 1.1V
2
Q35 *BSS138_NL/SOT23
0 1 1.0V
2
CPU_LDT_REQ#_CPU 1 3 +1.5VSUS R238 1K/F_4
CPU_LDT_REQ# [9,11]
R235 *1K/F_4
CPU_LDT_RST# 1 3 CPU_LDT_RST_HTPA#
+1.5V 1 0 0.9V
Q23
R462 *0_4 BSS138_NL/SOT23 R240 1K/F_4 1 1 0.8V
+1.5VSUS
1
G1 +1.5V R237 *1K/F_4
The RS880 family does not support CLMC architecture *SHORT_PAD1 S1G4
CPU_SVC
The LDTREQ# connection from the CPU to ALLOW_LDTSTOP CPU_SVD
CPU_SVC [37]
for debug only CPU_SVD [37]
2
of the Northbridge is no longer required. CPU_PWRGD_SVID_REG
CPU_PWRGD_SVID_REG [11,37]
+1.5VSUS R231 *220_4
S1g4 does not support MEMHOT# R232 *220_4
R244 *220_4
3
+1.5VSUS R101 *10K_4
S1G4
2
R100 *1K_4 Q12 2 CPUTEST24 R428 1K/F_4
+1.5VSUS
CPU_MEMHOT_L# 3 1
*MMBT3904
CPU_MEMHOT# [5,6,11]
[34] HWPG
Q8008
FDV301N HDT Connector CPUTEST23
CPUTEST20
CPUTEST22
R426
R427
R429
1K/F_4
1K/F_4
1K/F_4
C01 CPUTEST12 R188 1K/F_4
1
+1.5VSUS R417 *10K_4 R8191 1K_4 CPUTEST15 R227 *300/F_4
1 2 CPUTEST14 R243 *300/F_4
R425 1K_4 3 4 CPUTEST19 R233 1K/F_4
+1.5VSUS
2
A Q32 R8189 CPUTEST18 R230 1K/F_4 A
C01 5 6
MMBT3904 C01 100K_6 CPU_DBREQ# 7 8 CPUTEST21 R139 1K/F_4
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