Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 7551G_Wistron_JE70-DN_RevSB
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5 4 3 2 1
Block Diagram
DDR3 800/1066/1333MHz CLK GEN. 3
AMD Champlain CPU
D
DIMM1 16 S1G4 (45W) CRT ICS9LPRS480BKLFT 71.09480.A03 D
20 RTM880N-796-VB-GRT 71.00880.A03
800/1066/1333MHz
DDR3 800/1066/1333MHz
638-Pin uFCPGA638
4,5,6,7
LCD
800/1066/1333 MHz 19
DIMM2 & DIMM3 17
HDMI
OUT
HT 3.0 21
IN
16X16
Madison & Park
DDR3
North Bridge ATI VRAM
16X
AMD RS880M 52,53,54,55,56 57, 58, 59, 60
CPU I/F LVDS, CRT I/F PCI EXPRESS GRAPHIC
INTEGRATED GRAHPICS PCIex1 LAN
Giga LAN TXFM RJ45
27 27
C
21*21*1.84mm BCM57780 26 C
INT MIC 8,9,10
30 Mini Card
A-Link WLAN 33
MIC In Codec AZALIA 4X1
ALC272 Mini Card
30
28
Line Out South Bridge
AMD SB820
LPC BUS
30
USB 2.0/1.1 ports
ETHERNET (10/100/1000Mb) BIOS
High Definition Audio KBC MXIC
LPC
ATA 66/100 Novoton MX25L1605
DEBUG
NPCE781B 37 CONN.37
B ACPI 1.1 36 B
INT.SPKR LPC I/F
30 OP AMP PCI/PCI BRIDGE
23*23*1.92mm Touch INT.
29
11,12,13,14,15 Pad 38 KB 36
CardReader Project code: 91.4HP01.001
MS/MS Pro/xD
AU6437 PCB P/N : 48.4HP01.0SB
/MMC/SD
5 in 1
SATA USB 32 32 REVISION : 09929-SB
22
USB Daughter Board
SATA 3 Port 25 USB Board
ODD SATA
A 23 JE70-DN A
Blue Tooth Camera
24 19 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
USB Title
1 Port 25 BLOCK DIAGRAM
Size Document Number Rev
A3
JE70-DN SB
Date: Monday, December 07, 2009 Sheet 1 of 63
5 4 3 2 1
5 4 3 2 1
page36
EC Functional Strap Definitions
Signal Comment
Test Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
determine the device operation mode as follows:
TEST# No pull-down resistor: Normal operation mode (XORTR and TRIST strap pins
are ignored).
pin110
10 K external pull-down resistor:Test mode (ICT or XOR-Tree Test mode,
D SYSTEM DC/DC page9 according to XORTR and TRIST strap pins). D
RT8223 45 XOR-Tree Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
INPUTS OUTPUTS STRAP_DEBUG_BUS_GPIO_ENABLEb select the XOR-Tree Test mode, if TEST is strapped low:
5V_S5(5A) Enables the Test Debug Bus using GPIO.(PIN: RS780M--> VSYNC#) XORTR# No pull-down resistor: Not allowed if TEST pin is strapped low.
DCBATOUT
3D3V_S5(5A) 1 :Disable 0 : Enable
* pin111 10 K external pull-down resistor:XOR-Tree Test mode .Note: TRIST strap
pin must be left unconnected.
SYSTEM DC/DC RS780: Enables Side port memory ( RS880 use HSYNC#)
ICT Mode Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to
RT8209E 46 *1 :Disable 0 : Enable select the ICT Test mode, if TEST is strapped low:
INPUTS OUTPUTS No pull-down resistor: Not allowed if TEST pin is strapped low.
dware Default Values
SUS_STAT# TRIST# 10 K external pull-down resistor:ICT Test mode (see Section 3.4.1 on page
DCBATOUT 1D5V_S3 Selects Loading of STRAPS From EEPROM 53), forces the device to float its output and I/O pins.Note: XORTR strap pin
pin112 must be left unconnected.
*1 : Bypass the loading ofstrap values from EEPROM if connected,
0 : I2C Master can load
EEPROM straps and use Har
SYSTEM DC/DC or use default values if not connected JTAG Select. Sampled at VCC Power-Up reset or VCC_POR Input reset, to select
RT8015A 47 the JTAG signals to device pins (see Table 4 on page 35 for details).
INPUTS OUTPUTS JEN0#, JENK# Both JEN0 and JENK, are pulled to 1 by an internal resistor
page15 pin49,53 The external 10 K pull-down resistor must be connected to GND.
DCBATOUT 1D8V_S0
Shared Host BIOS Memory. Sampled at VCC Power-Up reset or VCC_POR Input
C RT9025 48 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 reset, to determine the state of the shared BIOS memory. C
SHBM
No pull-down resistor:Disable the shared BIOS memory.
5V_S5 1D05V_S0 PULL USE PCI DISABLE ILA USE FC USE DEFAULT DISABLE PCI pin83
HIGH PLL AUTORUN PLL PCIE STRAPS MEM BOOT 10 K external pull-down resistor:Enable the shared BIOS memory
RT9161 48 DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT Port80 (SDP) Visibility Mode Select. Sampled at VCC Power-Up reset or
VCC_POR Input reset, to select the Visibility mode for the Port80 (SDP).
3D3V_S0 2D5V_S0 SDP_VIS#
(200mA) PULL BYPASS ENABLE ILA BYPASS FC USE EEPROM ENABLE PCI No pull-down resistor: SDP in Normal mode
LOW PCI PLL AUTORUN PLL PCIE STRAPS MEM BOOT pin41
RT9025 48 10 K external pull-down resistor:SDP in Visibility mode.
3D3V_S0 1V_VGA XOR_OUT XOR-Tree Output. The device pins are internally connected in a XOR-tree structure
(1.2A)
Note: SB820 has 15K internal PU FOR PCI_AD[27:23] pin35
RT9025,RT8209E 47
3D3V_S5 1D1V_S5
page15 page12 USB
5V_S5 1D1V_S0
Pair Device
PCI_CLK1 PCI_CLK2 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 AZ_SDOUT GPIO200 GPIO199
CHARGER
BQ24745 49 ALLOW Watchdog USE non_Fusion EC CLKGEN LOW POWER
12 MINI2 CARD
PULL
PCIE Gen2 Timer DEBUG CLOCK MODE ENABLED ENABLED MODE H,H = Reserved 11 NC
HIGH
B INPUTS OUTPUTS DEFAULT Enabled STRAP DEFAULT DEFAULT
B
H,L = SPI ROM 10 NC
CHG_PWR 9 CCD
18V 6.0A PULL FORCE Watchdog IGNORE FUSION EC CLKGEN PERFORMANCE L,H = LPC ROM (Default) 8 NC
DCBATOUT LOW PCIE Gen1 Timer DEBUG CLOCK MODE DISABLED DISABLED MODE
UP+5V L,L = FWH ROM 7 Bluetooth
Disabled STRAP
5V 100mA DEFAULT DEFAULT DEFAULT DEFAULT
6 USB3
CPU DC/DC OCP3# 5 USB2
ISL6265HR 44 4 CardReader
NOTE: SB820 HAS INTERNAL 15K PULL UP RESISTOR FOR RTCCLK
INPUTS OUTPUTS 3 NC
VCC_CORE_S0_0 OCP2# 2 USB4
0~1.55V 18A PCB STACKUP Daughter Board 1 MINI1 CARD
VCC_CORE_S0_1 TOP Power Board(09744-SB) OCP0# 0 USB1
DCBATOUT
0~1.55V 18A
VCC
VDDNB
0~1.55V 18A Daughter Board JE70-DN
S
A
Power Board(09741-SB) A
S Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
GND Taipei Hsien 221, Taiwan, R.O.C.
Daughter Board
Title
BOTTOM Power Board(09742-SB)
Reference
Size Document Number Rev
A3
JE70-DN SB
Date: Thursday, November 19, 2009 Sheet 2 of 63
5 4 3 2 1
5 4 3 2 1
3D3V_S0 3D3V_CLK_VDD
DY DY 3D3V_S0
1 R556 2 R603
Do Not Stuff 1 2 3D3V_48MPW R_S0
1
1
1
1
1
1
1
1
1
C808 C809 C519 C814 C825 C817 C512 C812 C517
1
1
SC10U10V5ZY-1GP
SC10U10V5ZY-1GP
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Do Not Stuff
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
2R3J-GP C840 C838
DY SC1U10V2KX-1GP
2
2
2
2
2
2
2
2
2
Do Not Stuff
Do Not Stuff
2
2
3000mA.80ohm
D D
CLK_PCIE_PEG 1 2
DY EC62 Do Not Stuff
CLK_PCIE_PEG# 1 2
DY EC63 Do Not Stuff
3D3V_S0 1D1V_CLK_VDDIO
C830 CLK_NB_GFX 1 2
1 R565 2 R591 SC12P50V2JN-L1-GP DY EC65 Do Not Stuff
Do Not Stuff 1 DY 2 1 2 CLK_NB_GFX# 1 2
1
1
1
1
1
1
1
C816 C820 C518 C813 C516 C815 C515 3D3V_CLK_VDD DY EC64 Do Not Stuff
1
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SC10U6D3V3MX-GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
SCD1U10V2KX-4GP
Do Not Stuff 82.30005.901
U75 X7 CLK_PCIE_SB 1 2
2
2
2
2
2
2
2
1D1V_CLK_VDDIO X-14D31818M-37GP C833 DY EC69 Do Not Stuff
26 61 GEN_XTAL_IN CLK_PCIE_SB# 1 2
2
VDDATIG X1 GEN_XTAL_OUT SC12P50V2JN-L1-GP EC68 Do Not Stuff
25 VDDATIG_IO X2 62 1 2 DY
48 CLK_PCIE_LAN 1 2
VDDCPU EC67 Do Not Stuff
47 VDDCPU_IO SMBCLK 2 SMBC0_SB 12,16,17 DY
3 CLK_PCIE_LAN# 1 2
SMBDAT SMBD0_SB 12,16,17
16 DY EC66 Do Not Stuff
VDDSRC
17 VDDSRC_IO
11 30 CLK_NB_GPPSB 1 2
3D3V_CLK_VDD VDDSRC_IO ATIG0T_LPRS CLK_PCIE_PEG 52 EC71 Do Not Stuff
ATIG0C_LPRS 29 CLK_PCIE_PEG# 52 DY
35 28 CLK_NB_GPPSB# 1 2
VDDSB_SRC ATIG1T_LPRS EC70 Do Not Stuff
34 VDDSB_SRC_IO ATIG1C_LPRS 27 CLK_NB_GFX 9 DY
CLK_NB_GFX# 9
1 R303 2 40 VDDSATA
CLK_PCIE_MINI1 1 2
C Do Not Stuff 4 23 CLKREQ0# DY EC73 Do Not Stuff C
VDD CLKREQ0# TP168 Do Not Stuff
1
C826 55 45 LAN_CLKREQ# LAN_CLKREQ# 26 CLK_PCIE_MINI1# 1 2
SC1U10V2KX-1GP VDD_REF VDDHTT CLKREQ1# CLKREQ2# EC72 Do Not Stuff
56 VDDREF CLKREQ2# 44 TP166 Do Not Stuff DY
3D3V_48MPW R_S0 63 39 W LAN_CLKREQ# W LAN_CLKREQ# 33
2
VDD48 CLKREQ3# MIN2_CLKREQ# CLK_PCIE_MINI2
CLKREQ4# 38 MIN2_CLKREQ# 33 1 2
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