Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire 8943G_Quanta_ZYA_Rev1A
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5 4 3 2 1
ZYA SYSTEM BLOCK DIAGRAM GPU CORE PWR
ISL6264 P43
CHARGER
ISL88731 P37
GPU IO PWR 3/5V SYS PWR
ISL62827 P44 RT8206 P38
D DISCHARGER CPU CORE PWR D
+3V,+ 5V,+1.5V,+1.05V,+1.1V_VTT
P46 ISL62882 P39
CLOCK GENERATOR Fan Driver
SELGO: SLG8SP595V
BCLK: 133MHz
PEG_CLK: 100MHz
DPLL_REF_SSCLK: 120MHz
intel (PWM Type) +1.0V/+1.8V
CPU VTT
ARD: 1.05V
CFD: 1.1V
RT9018A + TPS54418
X'TAL
14.318MHz P3
P35 P47 UP61111AQDD P40
CPU VGFX_AXG VTT 1.05V
DDR SYSTEM MEMORY
Dual Channel Arrandale (SG)* ISL62881 P45 UP61111AQDD P41
DDR III Clarksfield (Discrete)
SO-DIMM 0 800/ 1066 MHz
SO-DIMM 1 THERMAL DDR3 PWR
800 MT/s 1066 MT/s PROTECTION P47 RT8207A P42
SO-DIMM 2
SO-DIMM 3
rPGA 989
P14, 15, 16, 17 (37.5mm X 37.5mm)
PCI-E
X16
P4.5.6.7 PCIE
FDI DMI
2.5GT/s
AMD GPU
Broadway-Pro / Madison-Pro
HDMI
CRT HDMI P28
C
* [Arrandale Only]
X4 DMI interface
1GB (64Mb x 32 IO x 8 pcs)
LVDS
C
P19,20,21,22,23,24,25,26
CRT
Graphics Interfaces
FDI DMI X'TAL P27
27.0MHz LVDS_CRT
HDD (SATA) *2
intel INT_CRT *[Arrandale Only] Switch Grapgics
Note: LVDS
HM55 does not support USB 6 & 7
P27
HM55 does not support SATA 2 & 3
P29
SATA0
INT_LVDS *[Arrandale Only] P27
SATA
SATA5 3.0 GT/s
Ibex Peak_M
eSATA Conn. eSATA Buffer ODD (SATA) SATA1
P34
P29
USB 9 (Debug) P34 PCI-Express
PCI-E
2.5GT/s
SATA4
USB Port x 5
USB 1, 3, 11, 12
(Debug)
P34 USB 2.0 676
mBGA 25mm) PCIE-1 & 2 Mini Card
B
USB WLAN / TV B
(27mm X RTC CLKOUT_PEG_1&3
X'TAL USB 10 & 13
P9
Bluetooth Azalia P8.9.10.11.12.13
32.768KHz
P30
HDA PCIE-5 PCIE-6
USB 4 P35
CLKOUT_PCIE2 CLKOUT_PEG_B
SPI LPC
CCD
USB 8 P27 X'TAL IEEE1394 & Atheros
32.768KHz
Media Cardreader Giga-LAN
Audio CODEC SPI ROM EC (WPC781) AR8151
FingerPrint 4MB x1 (Basic ME+Braidwood) OZ888
ALC669X P31 P9 P33 X'TAL P34 & Daughter Board X'TAL
USB 2 P35 P36 24.576MHz 25MHz
IEEE1394a Card Reader Transformer
Daughter Board
SPI ROM connector P33 Connector P33
P36
A RJ45 Connector A
Front Stereo Amp Center Mono Amp Rear Audio Amp Sub-Amplifier Daughter Board
(G1453L/ 2W+2W) (G1442/ 2W) & Head phone (TPA311D1) Touch Pad
P32 P31 AN12947A P30 P32 P35
SSID: DISCRETE: 030A
SSID: SWITCH GFX: 0308 Quanta Computer Inc.
Front Speaker Center Speaker Speaker S/PDIF SUBWOOFER Line in MIC Jack Int. D-MIC PROJECT : ZYA
K/B COON. CIR SVID: 1025 Size Document Number Rev
P32 P32 P30 P30 P32 P32 P32 P32 P36 P36
1A
ZYA Block Diagram
Date: Wednesday, January 20, 2010 Sheet 1 of 50
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A +3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC
Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V
H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.
PROJECT : ZYA
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Wednesday, January 20, 2010 Sheet 2 of 50
1 2 3 4 5 6 7 8
5 4 3 2 1
REV : B chenge pin define for B-test
80mA(20mil) +1.05V
C465 close L36
+1.5V 150mA(20mil) C10050 close L35 U20
BKP1608HS181T_6_1.5A L29
L26 BLM18AG601/0.2A_6 +1.5V_CLK 1 VDD_DOT +VDDIO_CLK C534 C558 C557
17 VDD_SRC VDD_SRC_I/O 15
D 180ohm/1.5A 24 18 D
R402 C579 C575 C535 C565 VDD_CPU VDD_CPU_I/O .1u/16V_4 .1u/16V_4 10u/Y5V_8
5 VDD_27
*0_6 *10u/6.3V_8 .1u/16V_4 .1u/16V_4 .1u/16V_4 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK [10]
DOT_96# 4 CLK_BUF_DREFCLK# [10]
+3V CLK_SDATA 31
CLK_SCLK SDA R395 B@0_4
32 SCL 27M 6 27M_CLK [20]
L31 BLM18AG601/0.2A_6 +3V_CLK 7 R396 *0_4
27M_SS For ATI suggest
R381 33_4 CPU_SEL30 10
[10] CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_DREFSSCLK [10]
SRC_1#/SATA# 11 CLK_BUF_DREFSSCLK# [10]
C10000 close L72 C584 C533 C560 C556 33p_4 13
SRC_2 CLK_BUF_PCIE_3GPLL [10]
10u/6.3V_8 0.1u/10V_4 0.1u/10V_4 14
SRC_2# CLK_BUF_PCIE_3GPLL# [10]
1
XTAL_IN 28
Y2 XTAL_IN
Switch CLK_BUF_DREFSSCLK and CLK_BUF_PCIE_3GPLL on ver B(SATA)
XTAL_OUT 27 16 R354 10K_4
14.318MHZ XTAL_OUT *CPU_STOP#
2
C546 33p_4 2 20
VSS_DOT CPU_1 TP23
C 8 19 +3V C
VSS_27 CPU_1# TP21
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK [10]
12 22
21
VSS_SRC
VSS_CPU
CPU_0# CLK_BUF_BCLK# [10]
CK_PWRGD_R
For EMI
SLG8SP595V STUFF L35 (default) 26 VSS_REF CKPWRGD/PD# 25
33 CLK_ICH_14M C561 *10p/50V_4
GND 27M_CLK C580 *10p/50V_4
SLG8SP585V STUFF R10000
SLG8LV595V
+3V
CPU_CLK select SMBus +3V CLK Enable
+1.05V R343
1K/F_4
B B
R399
R386 4.7K_4 CK_PWRGD_R
2
*4.7K_4
3
Q20
3 1 CLK_SDATA CLK_SDATA [14,15,16,17,30] 2N7002K
[10] ICH_SMBDATA
CPU_SEL
Q23 [39] VR_PWRGD_CK505# 2 R345
2N7002K 100K/F_4
R388
4.7K_4
+3V
1
R400
4.7K_4
A
Quanta Computer Inc. A
2
0 1
3 1 CLK_SCLK
CPU_SEL CPU0/1=133MHz CPU0/1=100MHz
[10] ICH_SMBCLK CLK_SCLK [14,15,16,17,30] PROJECT : ZYA
(default) Q24 Size Document Number Rev
2N7002K 1A
Clock Generator
Date: Wednesday, January 20, 2010 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
REV : B no stuff for B-test
Processor Compensation Signals
U34A U34B CPU_DDR3_DRAMRST#
B26 PEG_COMP R527 49.9/F_4 R580 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3
PEG_ICOMPO A26 BCLK A16 CLK_CPU_BCLK [11]
MISC
MISC
A24 B27 R583 20/F_4 H_COMP2 AT24 B16 CLK_CPU_BCLK# [11]
[8] DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 PEG_RBIAS R520 750/F_4 R481
[8] DMI_TXN1 DMI_RX#[1] PEG_RBIAS
CLOCKS
B22 PEG_RXN[0..15] [19] R132 49.9/F_4 H_COMP1 G16 AR30 BCLK_ITP_P T57
[8] DMI_TXN2 DMI_RX#[2] COMP1 BCLK_ITP
A21 K35 PEG_RXN0 AT30 BCLK_ITP_N T56 *100K_4
D [8] DMI_TXN3 DMI_RX#[3] PEG_RX#[0] BCLK_ITP# D
J34 PEG_RXN1 R588 49.9/F_4 H_COMP0 AT26
PEG_RX#[1] PEG_RXN2 COMP0
[8] DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33 PEG_CLK E16 CLK_PCIE_3GPLL [10]
D23 G35 PEG_RXN3 D16 CLK_PCIE_3GPLL# [10]
[8] DMI_TXP1 DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
DMI
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