Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire One AO753_Wistron_JV10-CS_Rev-1
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5 4 3 2 1
Project code:91.4GS01.001
JV10-CS Block Diagram
SYSTEM DC/DC
PCB P/N :48.4GS01.0SA RT8223
INPUTS OUTPUTS
REVISION :09918-1 5V_S5
DCBATOUT
Clock Generator 3D3V_S5
Intel CPU 42
ICS9LRS3197AKLFT DDRIII Slot 0
D 3 800/1066/1333 21
DDRIII Channel A SFF SYSTEM DC/DC D
RT8209E
INPUTS OUTPUTS
DDRIII Slot 1 DDRIII Channel B 4,5,..,10,11
800/1066/1333 22
DCBATOUT 1D5V_S3
43
FDIx8 DMIx4 SYSTEM DC/DC
RT8209B
24
INPUTS OUTPUTS
RGB CRT
CRT
Mini-Card INTEL DCBATOUT 1D05V_S0
PCIE+USB 2.0 44
WLAN & 3G
33 LVDS 2CH
LCD
PCH WXGA+ 23 SYSTEM DC/DC
RT9026
14 USB 2.0/1.1 ports INPUTS OUTPUTS
Giga LAN Digital Display HDMI
RJ45 ETHERNET (10/100/1000Mb) 25
PCIE
C
CONN AR8151 High Definition Audio 5V_S5 DDR_VREF_S3
43
C
32 31 6 SATA ports
8 PCIE ports
WEBCAM 23 CPU DC/DC
ACPI 1.1
TPS51611
INPUTS OUTPUTS
LPC I/F BLUETOOTH
35 MIC IN HD AUDIO 38
PCI/PCI BRIDGE DCBATOUT VCC_CORE
CODEC AZALIA
41
23 INT MIC ALC271X USB 2.0 USB x 3
34
29,38
INTERSIL CHARGER
ISL88731A
Card Reader
35 SD/MMC
LINE OUT RTS5138 INPUTS OUTPUTS
30
MS/MS Pro/xD
31
DCBATOUT BT+
B SATA SATA HDD 45 B
28
Flash ROM
PCB STACKUP
12,13,...,19,20 SPI
2CH SPEAKER 4MB 37 TOP
35
Power
LPC Bus LPC debug 37
S
S
KBC GND
SPI
NPCE781B BOTTOM
36
JV10 CS
A A
Thermal Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Flash ROM Touch Int. Taipei Hsien 221, Taiwan, R.O.C.
36 Sensor
128KB PAD KB Title
G795 26 38
26 Block Diagram
CPU FAN Size Document Number Rev
A3
JV10-CS -1
Date: Friday, January 22, 2010 Sheet 1 of 50
5 4 3 2 1
5 4 3 2 1
PCH
Strapping Processor Strapping
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
CFG[4] Embedded 1: Disabled - No Physical Display Port attached to 1
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k Embedded DisplayPort.
- 10-k weak pull-up resistor. DisplayPort
D Presence 0: Enabled - An external Display Port device is D
INIT3_3V# Weak internal pull-down. Do not pull high. connected to the Embedded Display Port.
GNT3#/ Default Mode: Internal pull-up. CFG[3] PCI-Express Static 1: Normal Operation. 1
GPIO55 Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k weak Lane Reversal 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
pull-down resistor).
CFG[0] PCI-Express 1: Single PCI-Express Graphics 1
INTVRMEN High (1) = Integrated VRM is enabled Configuration 0: Bifurcation enabled
Low (0) = Integrated VRM is disabled Select
GNT0#, Default (SPI): Left both GNT0# and GNT1# floating. No pull up
GNT1# required. CFG[7] Reserved - Clarksfield (only for early samples pre-ES1) - 0
Temporarily used Connect to GND with 3.01K Ohm/5% resistor
Boot from PCI: Connect GNT1# to ground with 1-k pull-down
resistor. Leave GNT0# Floating. for early Note: Only temporary for early CFD samples
Clarksfield (rPGA/BGA) [For details please refer to the WW33
Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k samples. MoW and sighting report].
pull-down resistor. For a common motherboard design (for AUB and CFD),
GNT2#/ Default - Internal pull-up. the pull-down resistor should be used. Does not
GPIO53 Low (0)= Configures DMI for ESI compatible operation (for servers impact AUB functionality.
only. Not for mobile/desktops).
GPIO33 Default: Do not pull low.
Disable ME in Manufacturing Mode: Connect to ground with 1-k
pull-down resistor.
C C
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor.
Disable iTPM: Left floating, no pull-down required.
NV_ALE Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up
resistor.
Disable Danbury: Connect to ground with 4.7-k weak pull-down
resistor.
NC_CLE Weak internal pull-up. Do not pull low.
HAD_DOCK_EN# Low (0): Flash Descriptor Security will be overridden. Power Sequence
/GPIO[33] High (1) : Flash Descriptor Security will be in effect.
HDA_SDO Weak internal pull-down. Do not pull high.
HDA_SYNC Weak internal pull-down. Do not pull high.
U32 U40 U13
GPIO15 Weak internal pull-down. Do not pull high.
GPIO8 Weak internal pull-up. Do not pull low.
PM_SLP_S4# 1D5V_S3 ALL_PWRGD 1D05V_S0 VTT_PWRGD KBC IMVP_VR_EN
GPIO27 Default = Do not connect (floating)
High(1) = Enables the internal VccVRM to have a clean supply for
analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter RT8209E RT9025 NPCE781
B
circuits for analog rails. B
USB Table U77 PCH1C CPU1
PCIE Routing
Pair Device
LANE1 LAN IMVP_VR_EN CPU Core PWM CORE_PWRGD PCH H_PWRGD CPU
0 USB3
LANE2 MiniCard1 1 USB2
2 NC TPS51161 IBEXPEAK AUBURNDALE
3 MINICARD1
4 WECAM
PLT_RST#
5 NC
6 NC
7 NC ALL DEVICE
8 NC
JV10 CS
A 9 USB1(HS) A
10 NC
Wistron Corporation
11 Blue Tooth 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
12 MINIC2
Title
13 Cardreader
Table of Content
Size Document Number Rev
A3
JV10-CS -1
Date: Friday, January 22, 2010 Sheet 2 of 50
5 4 3 2 1
5 4 3 2 1
RFL1~4 EC MGB1005G601EBP R96
Do Not Stuff
Normal Pin 15,18----3.3V/1.05V
1D5V_S0 1 DY 2
68.00373.001 Low Power Pin 15,18---1.5V/1.05V
RFL1
MGB1005G601FBP-GP
-1 Normal Pin 1,17,24---3.3V/1.05V
3D3V_S0 2 1 3D3V_CK505 RFL2
D MGB1005G601FBP-GP Low Power Pin 1,17,24---1.5V/1.05V D
1
1
C241 C231
-1 2 1 1D05V_S0
SC1U10V2ZY-GP
SCD1U16V2ZY-2GP
2
2
R323
Do Not Stuff SAm
1 2 1D5V_S0 JV501D05V
DY JV703D3V
R104
-1 Do Not Stuff
RFL3 3D3V_CK505_IO 1 DY 2 3D3V_S0
Do Not Stuff
1
1
3D3V_S0 1 2 3D3V_CK505_1 C224 C230
14.31818M HZ
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SC1U10V2ZY-GP
SC1U10V2ZY-GP
CLK Normal C239 C227 C492
2
2
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